From: lkcl Date: Thu, 26 May 2022 17:07:41 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2072 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c06710d547273ed9efbecaea13c608ca83e02192;p=libreriscv.git --- diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index c8d962985..1afe4cd6a 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -610,18 +610,22 @@ More details can be found in [[sv/cr_ops]]. # pred-result mode -Predicate-result merges common CR testing with predication, saving on -instruction count. In essence, a Condition Register Field test -is performed, and if it fails it is considered to have been -*as if* the destination predicate bit was zero. -Arithmetic and Logical Pred-result is covered in [[sv/normal]] - -Ped-result mode may not be applied on CR ops. +Pred-result mode may not be applied on CR-based operations. Although CR operations (mtcr, crand, cror) may be Vectorised, predicated, pred-result mode applies to operations that have an Rc=1 mode, or make sense to add an RC1 option. +Predicate-result merges common CR testing with predication, saving on +instruction count. In essence, a Condition Register Field test +is performed, and if it fails it is considered to have been +*as if* the destination predicate bit was zero. Given that +there are no CR-based operations that produce Rc=1 co-results, +there can be no pred-result mode for mtcr and other CR-based instructions + +Arithmetic and Logical Pred-result, which does have Rc=1 or for which +RC1 Mode makes sense, is covered in [[sv/normal]] + # CR Operations CRs are slightly more involved than INT or FP registers due to the