From: Nicolai Hähnle <nicolai.haehnle@amd.com>
Date: Thu, 29 Nov 2018 23:37:07 +0000 (+0100)
Subject: amd/common/gfx10: pad shader buffers for instruction prefetch
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c067aaa580d3be44503329968110e2629a9b2da6;p=mesa.git

amd/common/gfx10: pad shader buffers for instruction prefetch

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---

diff --git a/src/amd/common/ac_rtld.c b/src/amd/common/ac_rtld.c
index ebf64d91658..55315913234 100644
--- a/src/amd/common/ac_rtld.c
+++ b/src/amd/common/ac_rtld.c
@@ -438,6 +438,25 @@ bool ac_rtld_open(struct ac_rtld_binary *binary,
 
 	binary->rx_size += rx_size;
 
+	if (i.info->chip_class >= GFX10) {
+		/* In gfx10, the SQ fetches up to 3 cache lines of 16 dwords
+		 * ahead of the PC, configurable by SH_MEM_CONFIG and
+		 * S_INST_PREFETCH. This can cause two issues:
+		 *
+		 * (1) Crossing a page boundary to an unmapped page. The logic
+		 *     does not distinguish between a required fetch and a "mere"
+		 *     prefetch and will fault.
+		 *
+		 * (2) Prefetching instructions that will be changed for a
+		 *     different shader.
+		 *
+		 * (2) is not currently an issue because we flush the I$ at IB
+		 * boundaries, but (1) needs to be addressed. Due to buffer
+		 * suballocation, we just play it safe.
+		 */
+		binary->rx_size = align(binary->rx_size + 3 * 64, 64);
+	}
+
 	return true;
 
 #undef report_if