From: Florent Kermarrec Date: Tue, 17 Mar 2015 11:04:00 +0000 (+0100) Subject: mibuild/platforms/versa: add ethernet clock constraints X-Git-Tag: 24jan2021_ls180~2099^2~173 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c06ab82f135d92bc56f6e5b459d5f5c47366416a;p=litex.git mibuild/platforms/versa: add ethernet clock constraints --- diff --git a/mibuild/platforms/versa.py b/mibuild/platforms/versa.py index 1a240ace..acdd9cfd 100644 --- a/mibuild/platforms/versa.py +++ b/mibuild/platforms/versa.py @@ -7,7 +7,7 @@ from mibuild.lattice.programmer import LatticeProgrammer _io = [ ("clk100", 0, Pins("L5"), IOStandard("LVDS25")), - ("rst_n", 0, Pins("A21"),IOStandard("LVCMOS33")), + ("rst_n", 0, Pins("A21"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("Y20"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("AA21"), IOStandard("LVCMOS33")), @@ -79,6 +79,13 @@ class Platform(LatticePlatform): def __init__(self): LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io) - + try: + self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0) + except ConstraintError: + pass + try: + self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0) + except ConstraintError: + pass def create_programmer(self): return LatticeProgrammer()