From: Luke Kenneth Casson Leighton Date: Wed, 26 Jun 2019 07:03:33 +0000 (+0100) Subject: add mv.x X-Git-Tag: convert-csv-opcode-to-binary~4406 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c06bed097aa8f212eb1f0c1b51b9557cd199d0cb;p=libreriscv.git add mv.x --- diff --git a/simple_v_extension/specification/discussion.mdwn b/simple_v_extension/specification/discussion.mdwn index 53c9b053a..d7bd96364 100644 --- a/simple_v_extension/specification/discussion.mdwn +++ b/simple_v_extension/specification/discussion.mdwn @@ -85,13 +85,13 @@ TODO: adapt to the above rules. swizzle needs a MV. see below for a potential way to use the funct7 to do a swizzle in rs2. -+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +|---------------|-------------|-------|----------|----------|--------|----------|--------|--------| | Encoding | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:2 | 1:0 | -+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ -| RV32-I-type + imm[11:0] + rs1[4:0] + funct3 | rd[4:0] + opcode + 0b11 | -+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ -| RV32-I-type + fn4[11:8] swizzle[7:0] + rs1[4:0] + 0b000 | rd[4:0] + OP-V + 0b11 | -+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +|---------------|-------------|-------|----------|----------|--------|----------|--------|--------| +| RV32-I-type | imm[11:0] | rs1[4:0] | funct3 | rd[4:0] | opcode | 0b11 | +|---------------|-------------|-------|----------|----------|--------|----------|--------|--------| +| RV32-I-type | fn4[11:8] swizzle[7:0] | rs1[4:0] | 0b000 | rd[4:0] | OP-V | 0b11 | +|---------------|-------------|-------|----------|----------|--------|----------|--------|--------| * funct3 = MV * OP-V = 0b1010111 @@ -101,27 +101,27 @@ swizzle needs a MV. see below for a potential way to use the funct7 to do a swi swizzle (only active on SV or P48/P64 when SUBVL!=0): -+-----+---+ +|-----|---| | 1:0 | x | -+-----+---+ +|-----|---| | 3:2 | y | -+-----+---+ +|-----|---| | 5:4 | z | -+-----+---+ +|-----|---| | 7:6 | w | -+-----+---+ +|-----|---| ---- potential MV.X? register-version of MV-swizzle? -+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +|---------------|-------------|-------|----------|----------|--------|----------|--------|--------| | Encoding | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:2 | 1:0 | -+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ -| RV32-R-type + funct7 + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0] + opcode + 0b11 | -+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ -| RV32-R-type + 0b0000000 + rs2[4:0] + rs1[4:0] + 0b001 | rd[4:0] + OP-V + 0b11 | -+---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +|---------------|-------------|-------|----------|----------|--------|----------|--------|--------| +| RV32-R-type | funct7 | rs2[4:0] | rs1[4:0] | funct3 | rd[4:0] | opcode | 0b11 | +|---------------|-------------|-------|----------|----------|--------|----------|--------|--------| +| RV32-R-type | 0b0000000 | rs2[4:0] | rs1[4:0] | 0b001 | rd[4:0] | OP-V | 0b11 | +|---------------|-------------|-------|----------|----------|--------|----------|--------|--------| * funct3 = MV.X * OP-V = 0b1010111 diff --git a/simple_v_extension/specification/mv.x.rst b/simple_v_extension/specification/mv.x.rst new file mode 100644 index 000000000..d6e713a03 --- /dev/null +++ b/simple_v_extension/specification/mv.x.rst @@ -0,0 +1,51 @@ +# MV.X and MV.swizzle + +swizzle needs a MV. see below for a potential way to use the funct7 to do a swizzle in rs2. + ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| Encoding | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:2 | 1:0 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| RV32-I-type + imm[11:0] + rs1[4:0] + funct3 | rd[4:0] + opcode + 0b11 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| RV32-I-type + fn4[11:8] swizzle[7:0] + rs1[4:0] + 0b000 | rd[4:0] + OP-V + 0b11 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ + +* funct3 = MV +* OP-V = 0b1010111 +* fn4 = 4 bit function. +* fn4 = 0b0000 - INT MV-SWIZZLE ? +* fn4 = 0b0001 - FP MV-SWIZZLE ? + +swizzle (only active on SV or P48/P64 when SUBVL!=0): + ++-----+---+ +| 1:0 | x | ++-----+---+ +| 3:2 | y | ++-----+---+ +| 5:4 | z | ++-----+---+ +| 7:6 | w | ++-----+---+ + +---- + +potential MV.X? register-version of MV-swizzle? + ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| Encoding | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:2 | 1:0 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| RV32-R-type + funct7 + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0] + opcode + 0b11 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ +| RV32-R-type + 0b0000000 + rs2[4:0] + rs1[4:0] + 0b001 | rd[4:0] + OP-V + 0b11 | ++---------------+-------------+-------+----------+----------+--------+----------+--------+--------+ + +* funct3 = MV.X +* OP-V = 0b1010111 +* funct7 = 0b0000000 - INT MV.X +* funct7 = 0b0000001 - FP MV.X +* funct7 = 0b0000010 - INT MV.swizzle to say that rs2 is a swizzle argument? +* funct7 = 0b0000011 - FP MV.swizzle to say that rs2 is a swizzle argument? + +question: do we need a swizzle MV.X as well? +