From: Florent Kermarrec Date: Wed, 11 Nov 2015 16:37:53 +0000 (+0100) Subject: boards/targets: remove papilio_pro/pipistrello X-Git-Tag: 24jan2021_ls180~2080 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c076c2cbd63dc4dfd6a356a09a5e792a2a8e4e7e;p=litex.git boards/targets: remove papilio_pro/pipistrello --- diff --git a/litex/boards/targets/papilio_pro.py b/litex/boards/targets/papilio_pro.py deleted file mode 100644 index 011232ec..00000000 --- a/litex/boards/targets/papilio_pro.py +++ /dev/null @@ -1,108 +0,0 @@ -#!/usr/bin/env python3 - -import argparse -from fractions import Fraction - -from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.boards.platforms import papilio_pro - -from litex.soc.cores.sdram.settings import MT48LC4M16 -from litex.soc.cores.sdram.phy import GENSDRPHY -from litex.soc.cores.flash import spi_flash -from litex.soc.integration.soc_sdram import * -from litex.soc.integration.builder import * - - -class _CRG(Module): - def __init__(self, platform, clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() - - f0 = 32*1000000 - clk32 = platform.request("clk32") - clk32a = Signal() - self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a) - clk32b = Signal() - self.specials += Instance("BUFIO2", p_DIVIDE=1, - p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE", - i_I=clk32a, o_DIVCLK=clk32b) - f = Fraction(int(clk_freq), int(f0)) - n, m, p = f.denominator, f.numerator, 8 - assert f0/n*m == clk_freq - pll_lckd = Signal() - pll_fb = Signal() - pll = Signal(6) - self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6", - p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL", - p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT", - i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0, - p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0., - i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1, - p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0., - i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd, - o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5, - o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5, - o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5, - o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5, - o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5, - o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5, - p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1, - p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1, - p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1, - p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1, - p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys - p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps - ) - self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk) - self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd) - - self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE", - p_INIT=0, p_SRTYPE="SYNC", - i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1, - i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk, - o_Q=platform.request("sdram_clock")) - - -class BaseSoC(SoCSDRAM): - csr_map = { - "spiflash": 16, - } - csr_map.update(SoCSDRAM.csr_map) - - def __init__(self, **kwargs): - platform = papilio_pro.Platform() - clk_freq = 80*1000000 - SoCSDRAM.__init__(self, platform, clk_freq, - cpu_reset_address=0x60000, - **kwargs) - - self.submodules.crg = _CRG(platform, clk_freq) - - if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = MT48LC4M16(clk_freq) - self.register_sdram(self.sdrphy, "minicon", - sdram_module.geom_settings, sdram_module.timing_settings) - - if not self.integrated_rom_size: - self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash2x"), - dummy=4, div=6) - self.flash_boot_address = 0x70000 - self.register_rom(self.spiflash.bus) - - -def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to the Papilio Pro") - builder_args(parser) - soc_sdram_args(parser) - args = parser.parse_args() - - soc = BaseSoC(**soc_sdram_argdict(args)) - builder = Builder(soc, **builder_argdict(args)) - builder.build() - - -if __name__ == "__main__": - main() diff --git a/litex/boards/targets/pipistrello.py b/litex/boards/targets/pipistrello.py deleted file mode 100644 index 748350e1..00000000 --- a/litex/boards/targets/pipistrello.py +++ /dev/null @@ -1,151 +0,0 @@ -#!/usr/bin/env python3 - -import argparse -from fractions import Fraction - -from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.boards.platforms import pipistrello - -from litex.soc.cores.sdram_settings import MT46H32M16 -from litex.soc.cores.sdram_phy import S6HalfRateDDRPHY -from litex.soc.cores.flash import spi_flash -from litex.soc.integration.soc_sdram import * -from litex.soc.integration.builder import * - - -class _CRG(Module): - def __init__(self, platform, clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sdram_half = ClockDomain() - self.clock_domains.cd_sdram_full_wr = ClockDomain() - self.clock_domains.cd_sdram_full_rd = ClockDomain() - - self.clk4x_wr_strb = Signal() - self.clk4x_rd_strb = Signal() - - f0 = Fraction(50, 1)*1000000 - p = 12 - f = Fraction(clk_freq*p, f0) - n, d = f.numerator, f.denominator - assert 19e6 <= f0/d <= 500e6 # pfd - assert 400e6 <= f0*n/d <= 1080e6 # vco - - clk50 = platform.request("clk50") - clk50a = Signal() - self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a) - clk50b = Signal() - self.specials += Instance("BUFIO2", p_DIVIDE=1, - p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE", - i_I=clk50a, o_DIVCLK=clk50b) - pll_lckd = Signal() - pll_fb = Signal() - pll = Signal(6) - self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6", - p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL", - p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT", - i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0, - p_DIVCLK_DIVIDE=d, p_CLKFBOUT_MULT=n, p_CLKFBOUT_PHASE=0., - i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1, - p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0., - i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd, - o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5, - o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5, - o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5, - o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5, - o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5, - o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5, - p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4, # sdram wr rd - p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//4, - p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2, # sdram dqs adr ctrl - p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2, # off-chip ddr - p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, - p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys - ) - self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk) - reset = platform.request("user_btn") - self.clock_domains.cd_por = ClockDomain() - por = Signal(max=1 << 11, reset=(1 << 11) - 1) - self.sync.por += If(por != 0, por.eq(por - 1)) - self.comb += self.cd_por.clk.eq(self.cd_sys.clk) - self.specials += AsyncResetSynchronizer(self.cd_por, reset) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0)) - self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk) - self.specials += Instance("BUFPLL", p_DIVIDE=4, - i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk, - i_LOCKED=pll_lckd, o_IOCLK=self.cd_sdram_full_wr.clk, - o_SERDESSTROBE=self.clk4x_wr_strb) - self.comb += [ - self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk), - self.clk4x_rd_strb.eq(self.clk4x_wr_strb), - ] - clk_sdram_half_shifted = Signal() - self.specials += Instance("BUFG", i_I=pll[3], o_O=clk_sdram_half_shifted) - clk = platform.request("ddram_clock") - self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE", - p_INIT=0, p_SRTYPE="SYNC", - i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1, - i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted, - o_Q=clk.p) - self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE", - p_INIT=0, p_SRTYPE="SYNC", - i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1, - i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted, - o_Q=clk.n) - - -class BaseSoC(SoCSDRAM): - csr_map = { - "spiflash": 16, - } - csr_map.update(SoCSDRAM.csr_map) - - def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs): - platform = pipistrello.Platform() - SoCSDRAM.__init__(self, platform, clk_freq, - cpu_reset_address=0x170000, # 1.5 MB - **kwargs) - - self.submodules.crg = _CRG(platform, clk_freq) - - if not self.integrated_main_ram_size: - sdram_module = MT46H32M16(self.clk_freq) - self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"), - sdram_module.memtype, - rd_bitslip=1, - wr_bitslip=3, - dqs_ddr_alignment="C1") - self.comb += [ - self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), - self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), - ] - self.register_sdram(self.ddrphy, "minicon", - sdram_module.geom_settings, sdram_module.timing_settings) - - if not self.integrated_rom_size: - self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash4x"), - dummy=10, div=4) - self.add_constant("SPIFLASH_PAGE_SIZE", 256) - self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) - self.flash_boot_address = 0x180000 - self.register_rom(self.spiflash.bus, 0x1000000) - - -soc_pipistrello_args = soc_sdram_args -soc_pipistrello_argdict = soc_sdram_argdict - - -def main(): - parser = argparse.ArgumentParser(description="LiteX SoC port to the Pipistrello") - builder_args(parser) - soc_pipistrello_args(parser) - args = parser.parse_args() - - soc = BaseSoC(**soc_pipistrello_argdict(args)) - builder = Builder(soc, **builder_argdict(args)) - builder.build() - - -if __name__ == "__main__": - main() -