From: Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com>
Date: Tue, 18 Jul 2017 15:31:38 +0000 (+0100)
Subject: cpu: Add missing rename of vector registers in the O3 CPU
X-Git-Tag: v19.0.0.0~2675
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0875dfc398780a05dec68bbe36a17f73a98e030;p=gem5.git

cpu: Add missing rename of vector registers in the O3 CPU

The introduction of a new vector register class broke rename in the O3
CPU due to an unhandled register class in
DefaultRename<Impl>::renameSrcRegs(). This patch fixes adds the
necessary handling to avoid a panic when the vector register file is
used.

Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4140
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index b9adcdff7..bc024f603 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1028,6 +1028,9 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
           case FloatRegClass:
             fpRenameLookups++;
             break;
+          case VecRegClass:
+            vecRenameLookups++;
+            break;
           case CCRegClass:
           case MiscRegClass:
             break;