From: lkcl <lkcl@web>
Date: Thu, 12 May 2022 11:56:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2261
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0a504f7fce9c2ca12366086490f9ba2b3e47c82;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 2e9f78e8e..79d0441d4 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -1010,7 +1010,16 @@ with the proposed microarchitecture: the differences however are key.
 
 * Both PEs and CPU run the exact same ISA.  A major complexity of 3D GPU
   and CUDA workloads  (JIT compilation etc) is eliminated, and, crucially,
-  the CPU may execute the PE's tasks, if needed.
+  the CPU may directly execute the PE's tasks, if needed. This simply
+  is not even remotely possible on GPU Architectures.
+* Where GPU Drivers use PCIe Shared Memory, the proposed architecture
+  deploys OpenCAPI.
+* Where GPUs are a foreign architecture and a foreign ISA, the proposed
+  architecture only narrowly misses being defined as big/LITTLE Symmetric
+  Multi-Processing (SMP) by virtue of the massively-parallel PEs
+  being a bit light on L1 Cache, in favour of large ALUs and proximity
+  to Memory, and require a modest amount of "helper" assistance with
+  their Virtual Memory Management.
 
 
 **Roadmap summary of Advanced SVP64**