From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 24 Jun 2020 17:09:10 +0000 (-0400)
Subject: Add more complete testbench for lsmem.py
X-Git-Tag: div_pipeline~286
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0bd2fa94d8c6ab6088278d51d547945df630d65;p=soc.git

Add more complete testbench for lsmem.py
---

diff --git a/src/soc/experiment/lsmem.py b/src/soc/experiment/lsmem.py
index 2760a55c..3b89163d 100644
--- a/src/soc/experiment/lsmem.py
+++ b/src/soc/experiment/lsmem.py
@@ -1,8 +1,9 @@
 from soc.minerva.units.loadstore import LoadStoreUnitInterface
-from nmigen import Signal, Module, Elaboratable
+from nmigen import Signal, Module, Elaboratable, Mux
 from soc.experiment.testmem import TestMemory # TODO: replace with TMLSUI
+import random
 
-from nmigen.back.pysim import Simulator
+from nmigen.back.pysim import Simulator, Settle
 
 
 class TestMemLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
@@ -14,14 +15,14 @@ class TestMemLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         m = Module()
 
         m.submodules.mem = mem = TestMemory(
-            self.regwid, self.addrwid, granularity=self.regwid//8)
+            self.regwid, self.addrwid, granularity=8)
 
         m.d.comb += [
             mem.rdport.addr.eq(self.x_addr),
             self.m_load_data.eq(mem.rdport.data),
 
             mem.wrport.addr.eq(self.x_addr),
-            mem.wrport.en.eq(self.x_store),
+            mem.wrport.en.eq(Mux(self.x_store, self.x_mask, 0)),
             mem.wrport.data.eq(self.x_store_data)
             ]
 
@@ -34,12 +35,24 @@ def write_to_addr(dut, addr, value):
     yield dut.x_addr.eq(addr)
     yield dut.x_store_data.eq(value)
     yield dut.x_store.eq(1)
+    yield dut.x_mask.eq(-1)
 
     yield
     yield dut.x_store.eq(0)
     while (yield dut.x_stall):
         yield
 
+def read_from_addr(dut, addr):
+    yield dut.x_addr.eq(addr)
+    yield dut.x_load.eq(1)
+    yield
+    yield dut.x_load.eq(0)
+    yield Settle()
+    while (yield dut.x_stall):
+        yield
+    assert (yield dut.x_valid)
+    return (yield dut.m_load_data)
+
 if __name__ == '__main__':
     m = Module()
     dut = TestMemLoadStoreUnit(regwid=32, addrwid=4)
@@ -50,15 +63,13 @@ if __name__ == '__main__':
 
     def process():
 
-        yield from write_to_addr(dut, 0xa, 0xbeef)
-        yield dut.x_addr.eq(0xa)
-        yield dut.x_load.eq(1)
-        yield
-        yield dut.x_load.eq(0)
-        #while not (yield dut.x_valid) and (yield dut.x_busy):
-            #yield
-        yield
-        yield
+        values = [random.randint(0, (1<<32)-1) for x in range(16)]
+
+        for addr, val in enumerate(values):
+            yield from write_to_addr(dut, addr, val)
+        for addr, val in enumerate(values):
+            x = yield from read_from_addr(dut, addr)
+            assert x == val
 
     sim.add_sync_process(process)
     with sim.write_vcd("lsmem.vcd", "lsmem.gtkw", traces=[]):