From: Branislav Brzak <branislav.brzak@syrmia.com>
Date: Tue, 20 Jun 2023 14:19:55 +0000 (+0200)
Subject: riscv: Ensure LE instruction fetching
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0c3bb70f2f13e07295041cdf24a4d2997fe99a4;p=binutils-gdb.git

riscv: Ensure LE instruction fetching

Currently riscv gdb code looks at arch byte order
when fetching instructions. This works when the
target is LE, but on BE arch it will byte swap the
instruction, while the riscv spec defines all
instructions are LE encoded regardless of
system memory endianess.
---

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 500279e1ae9..ae18eb64452 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -1812,7 +1812,6 @@ ULONGEST
 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
 			       CORE_ADDR addr, int *len)
 {
-  enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
   gdb_byte buf[RISCV_MAX_INSN_LEN];
   int instlen, status;
 
@@ -1833,7 +1832,8 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
 	memory_error (TARGET_XFER_E_IO, addr + 2);
     }
 
-  return extract_unsigned_integer (buf, instlen, byte_order);
+  /* RISC-V Specification states instructions are always little endian */
+  return extract_unsigned_integer (buf, instlen, BFD_ENDIAN_LITTLE);
 }
 
 /* Fetch from target memory an instruction at PC and decode it.  This can