From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 28 Sep 2020 11:25:17 +0000 (+0100)
Subject: switch off internal gpio (testing)
X-Git-Tag: 24jan2021_ls180~296
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0c549dbb052e8ee34a874008c79c2752e3af749;p=soc.git

switch off internal gpio (testing)
---

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 394913c2..820e5fd3 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,7 +28,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
-                         gpio=True, # for test purposes
+                         gpio=False, # for test purposes
                          debug="jtag", # set to jtag or dmi
                          units=units)