From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Sun, 24 Apr 2011 04:31:50 +0000 (-0700)
Subject: [sim] fixed divw/remw crashing simulator
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0cd05e70b496598033134acd5e038502d3763f0;p=riscv-isa-sim.git

[sim] fixed divw/remw crashing simulator
---

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index 5bf4db0..51c3d80 100644
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,9 +1,7 @@
 require_xpr64;
 if(RS2 == 0)
   RD = UINT64_MAX;
-// INT64_MIN/-1 corner case shouldn't occur in correct code, since
-// INT64_MIN is not a proper 32-bit signed value
-else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
+else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
   RD = RS1;
 else
   RD = sext32(int32_t(RS1) / int32_t(RS2));
diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index c338516..93c3858 100644
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,9 +1,7 @@
 require_xpr64;
-// INT64_MIN/-1 corner case shouldn't occur in correct code, since
-// INT64_MIN is not a proper 32-bit signed value
 if(RS2 == 0)
   RD = RS1;
-else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
+else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
   RD = 0;
 else
   RD = sext32(int32_t(RS1) % int32_t(RS2));