From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Jun 2020 11:13:27 +0000 (+0100)
Subject: move to common ALUHelpers for branch test_pipe_caller.py
X-Git-Tag: div_pipeline~438
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0d71345bb2f75e97946ba093edf3dae50b8f406;p=soc.git

move to common ALUHelpers for branch test_pipe_caller.py
---

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 199a5eba..b7d5ec8a 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -12,7 +12,7 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.regfile.regfiles import FastRegs
 
-from soc.fu.test.common import TestCase
+from soc.fu.test.common import TestCase, ALUHelpers
 from soc.fu.branch.pipeline import BranchBasePipe
 from soc.fu.branch.pipe_data import BranchPipeSpec
 import random
@@ -248,14 +248,10 @@ class TestRunner(FHDLTestCase):
 
         inp = yield from get_cu_inputs(dec2, sim)
 
-        if 'cia' in inp:
-            yield branch.p.data_i.cia.eq(inp['cia'])
-        if 'spr1' in inp:
-            yield branch.p.data_i.spr1.eq(inp['spr1'])
-        if 'spr2' in inp:
-            yield branch.p.data_i.spr2.eq(inp['spr2'])
-        if 'cr_a' in inp:
-            yield branch.p.data_i.cr.eq(inp['cr_a'])
+        yield from ALUHelpers.set_fast_cia(branch, dec2, inp)
+        yield from ALUHelpers.set_fast_spr1(branch, dec2, inp)
+        yield from ALUHelpers.set_fast_spr2(branch, dec2, inp)
+        yield from ALUHelpers.set_cr_a(branch, dec2, inp)
 
 
 if __name__ == "__main__":
diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 9d034f4b..302d1b79 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -43,3 +43,19 @@ class ALUHelpers:
             print ("extra inputs: so", so)
             yield alu.p.data_i.xer_so.eq(so)
 
+    def set_fast_cia(alu, dec2, inp):
+        if 'cia' in inp:
+            yield alu.p.data_i.cia.eq(inp['cia'])
+
+    def set_fast_spr1(alu, dec2, inp):
+        if 'spr1' in inp:
+            yield alu.p.data_i.spr1.eq(inp['spr1'])
+
+    def set_fast_spr2(alu, dec2, inp):
+        if 'spr2' in inp:
+            yield alu.p.data_i.spr2.eq(inp['spr2'])
+
+    def set_cr_a(alu, dec2, inp):
+        if 'cr_a' in inp:
+            yield alu.p.data_i.cr.eq(inp['cr_a'])
+