From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Nov 2018 11:36:43 +0000 (+0000)
Subject: convert rv_sl to same extra bitwidth arg
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0eea387a37e90292e4a65d775ee1f3f2797b93f;p=riscv-isa-sim.git

convert rv_sl to same extra bitwidth arg
---

diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index b196afa..515c221 100644
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,2 +1,2 @@
 require(rv_lt(SHAMT, sv_reg_t(xlen)));
-WRITE_RD(sext_xlen(rv_sl(RS1, SHAMT)));
+WRITE_RD(sext_xlen(rv_sl(RS1, SHAMT, 64)));
diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index c9495ab..87d65b7 100644
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sl(RS1, SHAMT)));
+WRITE_RD(sext32(rv_sl(RS1, SHAMT, 64)));
diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index 276e285..3a764a9 100644
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sl(RS1, rv_and(RS2, sv_reg_t(0x1FU)))));
+WRITE_RD(sext32(rv_sl(RS1, RS2, 32U)));