From: Florent Kermarrec Date: Thu, 16 Apr 2020 08:23:31 +0000 (+0200) Subject: bios/sdram: update/simplify with new exported LiteDRAM parameters. X-Git-Tag: 24jan2021_ls180~452 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c0f3710d66715f61cfed4a8cfdddfe7387ce907d;p=litex.git bios/sdram: update/simplify with new exported LiteDRAM parameters. --- diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c index dff35358..0d2e6d86 100644 --- a/litex/soc/software/bios/main.c +++ b/litex/soc/software/bios/main.c @@ -475,7 +475,7 @@ static void do_command(char *c) else if(strcmp(token, "sdrwr") == 0) sdrwr(get_token(&c)); #ifdef CSR_DDRPHY_BASE else if(strcmp(token, "sdrinit") == 0) sdrinit(); -#ifdef CSR_DDRPHY_WLEVEL_EN_ADDR +#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE else if(strcmp(token, "sdrwlon") == 0) sdrwlon(); else if(strcmp(token, "sdrwloff") == 0) sdrwloff(); #endif diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c index d79bb154..53333cd8 100644 --- a/litex/soc/software/bios/sdram.c +++ b/litex/soc/software/bios/sdram.c @@ -1,5 +1,5 @@ // This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq -// This file is Copyright (c) 2013-2019 Florent Kermarrec +// This file is Copyright (c) 2013-2020 Florent Kermarrec // This file is Copyright (c) 2018 Chris Ballance // This file is Copyright (c) 2018 Dolu1990 // This file is Copyright (c) 2019 Gabriel L. Somlo @@ -114,7 +114,7 @@ void sdrrdbuf(int dq) step = DFII_PIX_DATA_BYTES/2; } - for(p=0;p 32 show = (j%16 == 0); #endif for (k=0; k<128; k++) { @@ -368,7 +353,7 @@ int write_level(void) cdelay(10); csr_rd_buf_uint8(sdram_dfii_pix_rddata_addr[0], buf, DFII_PIX_DATA_BYTES); - if (buf[NBMODULES-1-i] != 0) + if (buf[SDRAM_PHY_MODULES-1-i] != 0) one_count++; else zero_count++; @@ -420,7 +405,7 @@ int write_level(void) sdrwloff(); ok = 1; - for(i=NBMODULES-1;i>=0;i--) { + for(i=SDRAM_PHY_MODULES-1;i>=0;i--) { if(delays[i] < 0) ok = 0; } @@ -428,7 +413,7 @@ int write_level(void) return ok; } -#endif /* CSR_DDRPHY_WLEVEL_EN_ADDR */ +#endif /* SDRAM_PHY_WRITE_LEVELING_CAPABLE */ static void read_delay_rst(int module) { /* sel module */ @@ -440,7 +425,7 @@ static void read_delay_rst(int module) { /* unsel module */ ddrphy_dly_sel_write(0); -#ifdef ECP5DDRPHY +#ifdef SDRAM_PHY_ECP5DDRPHY /* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */ ddrphy_dly_sel_write(0xFF); ddrphy_dly_sel_write(0); @@ -457,7 +442,7 @@ static void read_delay_inc(int module) { /* unsel module */ ddrphy_dly_sel_write(0); -#ifdef ECP5DDRPHY +#ifdef SDRAM_PHY_ECP5DDRPHY /* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */ ddrphy_dly_sel_write(0xFF); ddrphy_dly_sel_write(0); @@ -492,14 +477,14 @@ static void read_bitslip_inc(char m) static int read_level_scan(int module, int bitslip) { unsigned int prv; - unsigned char prs[DFII_NPHASES][DFII_PIX_DATA_BYTES]; + unsigned char prs[SDRAM_PHY_PHASES][DFII_PIX_DATA_BYTES]; unsigned char tst[DFII_PIX_DATA_BYTES]; int p, i; int score; /* Generate pseudo-random sequence */ prv = 42; - for(p=0;p 32 show = (i%16 == 0); #endif -#ifdef ECP5DDRPHY +#ifdef SDRAM_PHY_ECP5DDRPHY ddrphy_burstdet_clr_write(1); #endif command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA); cdelay(15); - for(p=0;p> module) & 0x1) != 1) working = 0; #endif @@ -569,7 +554,7 @@ static int read_level_scan(int module, int bitslip) static void read_level(int module) { unsigned int prv; - unsigned char prs[DFII_NPHASES][DFII_PIX_DATA_BYTES]; + unsigned char prs[SDRAM_PHY_PHASES][DFII_PIX_DATA_BYTES]; unsigned char tst[DFII_PIX_DATA_BYTES]; int p, i; int working; @@ -579,7 +564,7 @@ static void read_level(int module) /* Generate pseudo-random sequence */ prv = 42; - for(p=0;p> module) & 0x1) != 1) working = 0; #endif if(working) break; delay++; - if(delay >= ERR_DDRPHY_DELAY) + if(delay >= SDRAM_PHY_DELAYS) break; read_delay_inc(module); } delay_min = delay; /* Get a bit further into the working zone */ -#ifdef USDDRPHY +#if SDRAM_PHY_DELAYS > 32 for(i=0;i<16;i++) { delay += 1; read_delay_inc(module); @@ -648,35 +633,35 @@ static void read_level(int module) /* Find largest working delay */ while(1) { -#ifdef ECP5DDRPHY +#ifdef SDRAM_PHY_ECP5DDRPHY ddrphy_burstdet_clr_write(1); #endif command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA); cdelay(15); working = 1; - for(p=0;p> module) & 0x1) != 1) working = 0; #endif if(!working) break; delay++; - if(delay >= ERR_DDRPHY_DELAY) + if(delay >= SDRAM_PHY_DELAYS) break; read_delay_inc(module); } delay_max = delay; - if (delay_min >= ERR_DDRPHY_DELAY) + if (delay_min >= SDRAM_PHY_DELAYS) printf("-"); else printf("%02d+-%02d", (delay_min+delay_max)/2, (delay_max-delay_min)/2); @@ -919,7 +904,7 @@ int memtest(void) #ifdef CSR_SDRAM_BASE -#ifdef CSR_DDRPHY_BASE +#if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE) || defined(SDRAM_PHY_READ_LEVELING_CAPABLE) int sdrlevel(void) { int module; @@ -930,25 +915,26 @@ int sdrlevel(void) sdrsw(); - for(module=0; module