From: Eric Anholt Date: Fri, 22 Apr 2011 21:26:12 +0000 (-0700) Subject: i965/gen6: Move the depth/stencil state to state streaming. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c108a3f863c44b5e9760d4668148ef8ca7557b2f;p=mesa.git i965/gen6: Move the depth/stencil state to state streaming. Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index f905f4b40e0..fcc3a7941b6 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -716,11 +716,9 @@ struct brw_context /* gen4 */ drm_intel_bo *prog_bo; - /* gen6 */ - drm_intel_bo *depth_stencil_state_bo; - uint32_t state_offset; uint32_t blend_state_offset; + uint32_t depth_stencil_state_offset; uint32_t vp_offset; } cc; diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c index d1df1486ced..e47adf600a8 100644 --- a/src/mesa/drivers/dri/i965/brw_state_dump.c +++ b/src/mesa/drivers/dri/i965/brw_state_dump.c @@ -267,17 +267,15 @@ static void dump_cc_viewport_state(struct brw_context *brw) static void dump_depth_stencil_state(struct brw_context *brw) { + struct intel_context *intel = &brw->intel; const char *name = "DEPTH STENCIL"; struct gen6_depth_stencil_state *ds; uint32_t ds_off; - if (brw->cc.depth_stencil_state_bo == NULL) - return; - - drm_intel_bo_map(brw->cc.depth_stencil_state_bo, GL_FALSE); + drm_intel_bo_map(intel->batch.bo, GL_FALSE); - ds = brw->cc.depth_stencil_state_bo->virtual; - ds_off = brw->cc.depth_stencil_state_bo->offset; + ds = intel->batch.bo->virtual + brw->cc.depth_stencil_state_offset; + ds_off = intel->batch.bo->offset + brw->cc.depth_stencil_state_offset; state_out(name, ds, ds_off, 0, "stencil %sable, func %d, write %sable\n", ds->ds0.stencil_enable ? "en" : "dis", @@ -289,7 +287,7 @@ static void dump_depth_stencil_state(struct brw_context *brw) ds->ds2.depth_test_enable ? "en" : "dis", ds->ds2.depth_test_func, ds->ds2.depth_write_enable ? "en" : "dis"); - drm_intel_bo_unmap(brw->cc.depth_stencil_state_bo); + drm_intel_bo_unmap(intel->batch.bo); } static void dump_cc_state(struct brw_context *brw) diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 41e6b7c2869..5aec6feb990 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -92,7 +92,6 @@ static void brw_destroy_context( struct intel_context *intel ) dri_bo_release(&brw->wm.state_bo); dri_bo_release(&brw->wm.const_bo); dri_bo_release(&brw->cc.prog_bo); - dri_bo_release(&brw->cc.depth_stencil_state_bo); free(brw->curbe.last_buf); free(brw->curbe.next_buf); diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c index e4157b12eda..938f9148d22 100644 --- a/src/mesa/drivers/dri/i965/gen6_cc.c +++ b/src/mesa/drivers/dri/i965/gen6_cc.c @@ -158,18 +158,13 @@ static void upload_cc_state_pointers(struct brw_context *brw) OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, brw->cc.blend_state_offset | 1); - OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + brw->cc.depth_stencil_state_offset | 1); OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, brw->cc.state_offset | 1); ADVANCE_BATCH(); } - -static void prepare_cc_state_pointers(struct brw_context *brw) -{ - brw_add_validated_bo(brw, brw->cc.depth_stencil_state_bo); -} - const struct brw_tracked_state gen6_cc_state_pointers = { .dirty = { .mesa = 0, @@ -178,6 +173,5 @@ const struct brw_tracked_state gen6_cc_state_pointers = { CACHE_NEW_COLOR_CALC_STATE | CACHE_NEW_DEPTH_STENCIL_STATE) }, - .prepare = prepare_cc_state_pointers, .emit = upload_cc_state_pointers, }; diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c index 96e6eade6b7..775e1ce2c9c 100644 --- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c +++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c @@ -28,138 +28,68 @@ #include "brw_context.h" #include "brw_state.h" -struct brw_depth_stencil_state_key { - GLenum depth_func; - GLboolean depth_test, depth_write; - GLboolean stencil, stencil_two_side; - GLenum stencil_func[2], stencil_fail_op[2]; - GLenum stencil_pass_depth_fail_op[2], stencil_pass_depth_pass_op[2]; - GLubyte stencil_write_mask[2], stencil_test_mask[2]; -}; - static void -depth_stencil_state_populate_key(struct brw_context *brw, - struct brw_depth_stencil_state_key *key) +gen6_prepare_depth_stencil_state(struct brw_context *brw) { struct gl_context *ctx = &brw->intel.ctx; - const unsigned back = ctx->Stencil._BackFace; + struct gen6_depth_stencil_state *ds; - memset(key, 0, sizeof(*key)); + ds = brw_state_batch(brw, sizeof(*ds), 64, + &brw->cc.depth_stencil_state_offset); + memset(ds, 0, sizeof(*ds)); /* _NEW_STENCIL */ - key->stencil = ctx->Stencil._Enabled; - key->stencil_two_side = ctx->Stencil._TestTwoSide; - - if (key->stencil) { - key->stencil_func[0] = ctx->Stencil.Function[0]; - key->stencil_fail_op[0] = ctx->Stencil.FailFunc[0]; - key->stencil_pass_depth_fail_op[0] = ctx->Stencil.ZFailFunc[0]; - key->stencil_pass_depth_pass_op[0] = ctx->Stencil.ZPassFunc[0]; - key->stencil_write_mask[0] = ctx->Stencil.WriteMask[0]; - key->stencil_test_mask[0] = ctx->Stencil.ValueMask[0]; - } - if (key->stencil_two_side) { - key->stencil_func[1] = ctx->Stencil.Function[back]; - key->stencil_fail_op[1] = ctx->Stencil.FailFunc[back]; - key->stencil_pass_depth_fail_op[1] = ctx->Stencil.ZFailFunc[back]; - key->stencil_pass_depth_pass_op[1] = ctx->Stencil.ZPassFunc[back]; - key->stencil_write_mask[1] = ctx->Stencil.WriteMask[back]; - key->stencil_test_mask[1] = ctx->Stencil.ValueMask[back]; - } - - key->depth_test = ctx->Depth.Test; - if (key->depth_test) { - key->depth_func = ctx->Depth.Func; - key->depth_write = ctx->Depth.Mask; - } -} - -/** - * Creates the state cache entry for the given DEPTH_STENCIL_STATE state key. - */ -static drm_intel_bo * -depth_stencil_state_create_from_key(struct brw_context *brw, - struct brw_depth_stencil_state_key *key) -{ - struct gen6_depth_stencil_state ds; - drm_intel_bo *bo; - - memset(&ds, 0, sizeof(ds)); - - /* _NEW_STENCIL */ - if (key->stencil) { - ds.ds0.stencil_enable = 1; - ds.ds0.stencil_func = - intel_translate_compare_func(key->stencil_func[0]); - ds.ds0.stencil_fail_op = - intel_translate_stencil_op(key->stencil_fail_op[0]); - ds.ds0.stencil_pass_depth_fail_op = - intel_translate_stencil_op(key->stencil_pass_depth_fail_op[0]); - ds.ds0.stencil_pass_depth_pass_op = - intel_translate_stencil_op(key->stencil_pass_depth_pass_op[0]); - ds.ds1.stencil_write_mask = key->stencil_write_mask[0]; - ds.ds1.stencil_test_mask = key->stencil_test_mask[0]; - - if (key->stencil_two_side) { - ds.ds0.bf_stencil_enable = 1; - ds.ds0.bf_stencil_func = - intel_translate_compare_func(key->stencil_func[1]); - ds.ds0.bf_stencil_fail_op = - intel_translate_stencil_op(key->stencil_fail_op[1]); - ds.ds0.bf_stencil_pass_depth_fail_op = - intel_translate_stencil_op(key->stencil_pass_depth_fail_op[1]); - ds.ds0.bf_stencil_pass_depth_pass_op = - intel_translate_stencil_op(key->stencil_pass_depth_pass_op[1]); - ds.ds1.bf_stencil_write_mask = key->stencil_write_mask[1]; - ds.ds1.bf_stencil_test_mask = key->stencil_test_mask[1]; + if (ctx->Stencil._Enabled) { + int back = ctx->Stencil._BackFace; + + ds->ds0.stencil_enable = 1; + ds->ds0.stencil_func = + intel_translate_compare_func(ctx->Stencil.Function[0]); + ds->ds0.stencil_fail_op = + intel_translate_stencil_op(ctx->Stencil.FailFunc[0]); + ds->ds0.stencil_pass_depth_fail_op = + intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]); + ds->ds0.stencil_pass_depth_pass_op = + intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]); + ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0]; + ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0]; + + if (ctx->Stencil._TestTwoSide) { + ds->ds0.bf_stencil_enable = 1; + ds->ds0.bf_stencil_func = + intel_translate_compare_func(ctx->Stencil.Function[back]); + ds->ds0.bf_stencil_fail_op = + intel_translate_stencil_op(ctx->Stencil.FailFunc[back]); + ds->ds0.bf_stencil_pass_depth_fail_op = + intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]); + ds->ds0.bf_stencil_pass_depth_pass_op = + intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]); + ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back]; + ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back]; } /* Not really sure about this: */ - if (key->stencil_write_mask[0] || - (key->stencil_two_side && key->stencil_write_mask[1])) - ds.ds0.stencil_write_enable = 1; + if (ctx->Stencil.WriteMask[0] || + (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back])) + ds->ds0.stencil_write_enable = 1; } /* _NEW_DEPTH */ - if (key->depth_test) { - ds.ds2.depth_test_enable = 1; - ds.ds2.depth_test_func = intel_translate_compare_func(key->depth_func); - ds.ds2.depth_write_enable = key->depth_write; + if (ctx->Depth.Test) { + ds->ds2.depth_test_enable = 1; + ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func); + ds->ds2.depth_write_enable = ctx->Depth.Mask; } - bo = brw_upload_cache(&brw->cache, BRW_DEPTH_STENCIL_STATE, - key, sizeof(*key), - NULL, 0, - &ds, sizeof(ds)); - - return bo; -} - -static void -prepare_depth_stencil_state(struct brw_context *brw) -{ - struct brw_depth_stencil_state_key key; - - depth_stencil_state_populate_key(brw, &key); - - drm_intel_bo_unreference(brw->cc.depth_stencil_state_bo); - brw->cc.depth_stencil_state_bo = brw_search_cache(&brw->cache, - BRW_DEPTH_STENCIL_STATE, - &key, sizeof(key), - NULL, 0, - NULL); - - if (brw->cc.depth_stencil_state_bo == NULL) - brw->cc.depth_stencil_state_bo = - depth_stencil_state_create_from_key(brw, &key); + brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE; } const struct brw_tracked_state gen6_depth_stencil_state = { .dirty = { .mesa = _NEW_DEPTH | _NEW_STENCIL, - .brw = 0, + .brw = BRW_NEW_BATCH, .cache = 0, }, - .prepare = prepare_depth_stencil_state, + .prepare = gen6_prepare_depth_stencil_state, };