From: Jakub Jelinek Date: Sun, 2 Dec 2018 20:43:49 +0000 (+0100) Subject: re PR target/88278 (Fails to elide zeroing of upper vector register) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c10a94358fb8d0762c9eceb5d26125582fa7971f;p=gcc.git re PR target/88278 (Fails to elide zeroing of upper vector register) PR target/88278 * config/i386/sse.md (*vec_concatv4sf_0, *vec_concatv4si_0): New insns. * gcc.target/i386/pr88278.c: New test. * gcc.target/i386/pr53759.c: Don't expect vmovlps insn, expect vmovq instead. * gcc.target/i386/pr53759-2.c: New test. From-SVN: r266728 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 204a9fa27c0..d74c1a99024 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-12-02 Jakub Jelinek + + PR target/88278 + * config/i386/sse.md (*vec_concatv4sf_0, *vec_concatv4si_0): New insns. + 2018-12-02 Jeff Law * config/h8300/h8300.md (call, call_value): Drop mode from diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e2cae71d44a..1415c36930b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7248,6 +7248,17 @@ (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex") (set_attr "mode" "V4SF,V4SF,V2SF,V2SF")]) +(define_insn "*vec_concatv4sf_0" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (vec_concat:V4SF + (match_operand:V2SF 1 "nonimmediate_operand" "xm") + (match_operand:V2SF 2 "const0_operand" " C")))] + "TARGET_SSE2" + "%vmovq\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "DF")]) + ;; Avoid combining registers from different units in a single alternative, ;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "vec_set_0" @@ -14409,6 +14420,23 @@ (set_attr "prefix" "orig,maybe_evex,orig,orig,maybe_evex") (set_attr "mode" "TI,TI,V4SF,V2SF,V2SF")]) +(define_insn "*vec_concatv4si_0" + [(set (match_operand:V4SI 0 "register_operand" "=v,x") + (vec_concat:V4SI + (match_operand:V2SI 1 "nonimmediate_operand" "xm,?!*y") + (match_operand:V2SI 2 "const0_operand" " C,C")))] + "TARGET_SSE2" + "@ + %vmovq\t{%1, %0|%0, %1} + movq2dq\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "maybe_vex,orig") + (set_attr "mode" "TI") + (set (attr "preferred_for_speed") + (if_then_else (eq_attr "alternative" "1") + (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC") + (symbol_ref "true")))]) + ;; movd instead of movq is required to handle broken assemblers. (define_insn "vec_concatv2di" [(set (match_operand:V2DI 0 "register_operand" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 89dc430c1dc..a28b73ca5a7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2018-12-02 Jakub Jelinek + PR target/88278 + * gcc.target/i386/pr88278.c: New test. + * gcc.target/i386/pr53759.c: Don't expect vmovlps insn, expect vmovq + instead. + * gcc.target/i386/pr53759-2.c: New test. + * c-c++-common/gomp/cancel-1.c (f2): Add various taskloop related tests. diff --git a/gcc/testsuite/gcc.target/i386/pr53759-2.c b/gcc/testsuite/gcc.target/i386/pr53759-2.c new file mode 100644 index 00000000000..ddabb8481dc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr53759-2.c @@ -0,0 +1,16 @@ +/* PR target/53759 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ + +#include + +void +foo (__m128 *x, __m64 *y) +{ + __m128 a = _mm_add_ps (x[1], x[2]); + __m128 b = _mm_loadl_pi (a, y); + *x = _mm_add_ps (b, b); +} + +/* { dg-final { scan-assembler "vmovlps\[ \\t\]" } } */ +/* { dg-final { scan-assembler-not "vshufps\[ \\t\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr53759.c b/gcc/testsuite/gcc.target/i386/pr53759.c index d55316a79d4..c30592daf10 100644 --- a/gcc/testsuite/gcc.target/i386/pr53759.c +++ b/gcc/testsuite/gcc.target/i386/pr53759.c @@ -12,5 +12,6 @@ foo (__m128 *x, __m64 *y) *x = _mm_add_ps (b, b); } -/* { dg-final { scan-assembler "vmovlps\[ \\t\]" } } */ +/* { dg-final { scan-assembler "vmovq\[ \\t\]" } } */ +/* { dg-final { scan-assembler-not "vmovlps\[ \\t\]" } } */ /* { dg-final { scan-assembler-not "vshufps\[ \\t\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr88278.c b/gcc/testsuite/gcc.target/i386/pr88278.c new file mode 100644 index 00000000000..84d6e264332 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr88278.c @@ -0,0 +1,34 @@ +/* PR target/88278 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mno-sse3 -fgimple -masm=att" } */ +/* { dg-final { scan-assembler-times "movq\[ \t]+\\(" 2 } } */ +/* { dg-final { scan-assembler-not "punpcklqdq\[ \t]+" } } */ +/* { dg-final { scan-assembler-not "pxor\[ \t]+" } } */ + +typedef unsigned char v16qi __attribute__((vector_size(16))); +typedef unsigned char v8qi __attribute__((vector_size(8))); +typedef unsigned int v4si __attribute__((vector_size(16))); +typedef unsigned int v2si __attribute__((vector_size(8))); + +v16qi __GIMPLE foo (unsigned char *p) +{ + v8qi _2; + v16qi _3; + +bb_2: + _2 = __MEM (p_1(D)); + _3 = _Literal (v16qi) { _2, _Literal (v8qi) { _Literal (unsigned char) 0, _Literal (unsigned char) 0, _Literal (unsigned char) 0, _Literal (unsigned char) 0, _Literal (unsigned char) 0, _Literal (unsigned char) 0, _Literal (unsigned char) 0 } }; + return _3; +} + + +v4si __GIMPLE bar (unsigned int *p) +{ + v2si _2; + v4si _3; + +bb_2: + _2 = __MEM (p_1(D)); + _3 = _Literal (v4si) { _2, _Literal (v2si) { 0u, 0u } }; + return _3; +}