From: Andrew Cagney <cagney@redhat.com>
Date: Tue, 9 Dec 1997 05:46:48 +0000 (+0000)
Subject: Test/fix d10v RTE instruction.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c10ae9ad33b261235bc7b63b89a3bb6d0ca7a291;p=binutils-gdb.git

Test/fix d10v RTE instruction.
---

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c9d2fbb698d..5916f14127e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+Thu Oct 23 21:13:37 1997  Fred Fish  <fnf@cygnus.com>
+ 
+        * d10v-opc.c (d10v_opcodes): Correct entry for RTE.
+ 
 Mon Dec  8 11:21:07 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* disassemble.c: Remove disasm_symaddr() function.
diff --git a/sim/testsuite/d10v-elf/.Sanitize b/sim/testsuite/d10v-elf/.Sanitize
index dcdaad8a186..25ed0ae3635 100644
--- a/sim/testsuite/d10v-elf/.Sanitize
+++ b/sim/testsuite/d10v-elf/.Sanitize
@@ -15,6 +15,7 @@ t-msbu.s
 t-rac.s
 t-rachi.s
 t-rep.s
+t-rte.s
 t-mulxu.s
 t-sub.s
 t-subi.s
diff --git a/sim/testsuite/d10v-elf/t-rte.s b/sim/testsuite/d10v-elf/t-rte.s
new file mode 100644
index 00000000000..5ce31ddbf41
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-rte.s
@@ -0,0 +1,18 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = PSW_C|PSW_F0|PSW_F1
+	
+	ldi	r6, #success@word
+	mvtc	r6, bpc
+	ldi	r6, #PSW_BITS
+	mvtc	r6, bpsw
+
+test_rte:
+	RTE
+	exit47
+
+success:
+	checkpsw2 1 PSW_BITS
+	exit0