From: Alexandru Dutu <alexandru.dutu@amd.com>
Date: Mon, 24 Nov 2014 02:01:09 +0000 (-0800)
Subject: mem: Multi Level Page Table bug fix
X-Git-Tag: stable_2015_04_15~110
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c11bcb8119273ef91c40a25b8fd9471a887d0ee5;p=gem5.git

mem: Multi Level Page Table bug fix

The multi level page table was giving false positives for already mapped
translations. This patch fixes the bogus behavior.
---

diff --git a/src/mem/multi_level_page_table_impl.hh b/src/mem/multi_level_page_table_impl.hh
index 063e097c5..3d8cbe75d 100644
--- a/src/mem/multi_level_page_table_impl.hh
+++ b/src/mem/multi_level_page_table_impl.hh
@@ -151,14 +151,13 @@ MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr,
         if (walk(vaddr, true, PTE_addr)) {
             PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr);
             Addr entry_paddr = pTableISAOps.getPnum(PTE);
-            if (!clobber && entry_paddr == 0) {
-                pTableISAOps.setPnum(PTE, paddr >> PageShift);
-                pTableISAOps.setPTEFields(PTE);
-                p.write<PageTableEntry>(PTE_addr, PTE);
-                DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr);
-            } else {
+            if (!clobber && entry_paddr != 0) {
                 fatal("addr 0x%x already mapped to %x", vaddr, entry_paddr);
             }
+            pTableISAOps.setPnum(PTE, paddr >> PageShift);
+            pTableISAOps.setPTEFields(PTE);
+            p.write<PageTableEntry>(PTE_addr, PTE);
+            DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr);
 
             eraseCacheEntry(vaddr);
             updateCache(vaddr, TlbEntry(pid, vaddr, paddr));