From: lkcl <lkcl@web>
Date: Tue, 7 Jun 2022 00:30:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1928
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c12cb3f95c4c27a7320773fc0bacefea31fb0cd9;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index dec09925a..198877b22 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -204,6 +204,8 @@ Fields:
 
 Examples showing how all of these Modes operate exists in the online
 [SVP64 unit tests](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD)
+and the full pseudocode setting up all SPRs
+is in the [[openpower/isa/simplev]] page.
 
 In Indexed Mode, there are only 5 bits available to specify the GPR
 to use, out of 128 GPRs (7 bit numbering).  Therefore, only the top