From: Michael Meissner Date: Fri, 20 Sep 1996 01:42:15 +0000 (+0000) Subject: Make sure cmp{,eq,u}i use correct casts X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c12f5c678e2b93fa915a30698f952aedf57865b7;p=binutils-gdb.git Make sure cmp{,eq,u}i use correct casts --- diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 5baf78b6c61..1fbe0a3edbc 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,9 @@ +Thu Sep 19 21:38:20 1996 Michael Meissner + + * simops.c (OP_{401,2000000,601,3000000,23000000}): Get sign right + on comparisons. + (OP_401): Fix tracing information. + Thu Sep 19 10:30:22 1996 Michael Meissner * simops.c (SIZE_{PC,LINE_NUMBER}): New default sizes for output. diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index a1af4f90f8b..801ad80d448 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -874,9 +874,9 @@ OP_1403 () void OP_401 () { - trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID); + trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID); State.F1 = State.F0; - State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0; + State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0; trace_output (OP_FLAG); } @@ -886,7 +886,7 @@ OP_2000000 () { trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID); State.F1 = State.F0; - State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0; + State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0; trace_output (OP_FLAG); } @@ -896,7 +896,7 @@ OP_601 () { trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID); State.F1 = State.F0; - State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0; + State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0; trace_output (OP_FLAG); } @@ -926,7 +926,7 @@ OP_23000000 () { trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID); State.F1 = State.F0; - State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0; + State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0; trace_output (OP_FLAG); }