From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Jun 2020 05:00:38 +0000 (+0100)
Subject: whitespace / code-munge
X-Git-Tag: div_pipeline~542
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c135d338975880db2abf4d8d0d38d9ca2aa69723;p=soc.git

whitespace / code-munge
---

diff --git a/src/soc/scoreboard/issue_unit.py b/src/soc/scoreboard/issue_unit.py
index 44d76e89..27d6ff9d 100644
--- a/src/soc/scoreboard/issue_unit.py
+++ b/src/soc/scoreboard/issue_unit.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Cat, Array, Const, Repl, Elaboratable
+from nmigen import Module, Signal, Cat, Const, Repl, Elaboratable
 from nmigen.lib.coding import Decoder
 
 from nmutil.picker import PriorityPicker
@@ -110,7 +110,8 @@ class IssueUnitGroup(Elaboratable):
         m.d.comb += self.busy_o.eq(~((~self.busy_i).bool()))
 
         # Picker only raises one signal, therefore it's also the fn_issue
-        m.d.comb += self.fn_issue_o.eq(pick.o & Repl(~self.busy_o, self.n_insns))
+        busys = Repl(~self.busy_o, self.n_insns)
+        m.d.comb += self.fn_issue_o.eq(pick.o & busys)
 
         return m