From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 26 Mar 2022 22:18:15 +0000 (+0000)
Subject: grr
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c13b571c49d30df49666b2459cb0cfc3c45225e6;p=ls2.git

grr
---

diff --git a/src/ls2.py b/src/ls2.py
index ea500f5..267f88f 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -273,7 +273,7 @@ class DDR3SoC(SoC, Elaboratable):
         # set up clock request generator
         pod_bits = 25
         if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
-            if fpga == ['isim']:
+            if fpga in ['isim']:
                 pod_bits = 2
             self.crg = ECP5CRG(clk_freq, pod_bits)
         if fpga in ['arty_a7']: