From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 12 Dec 2013 16:36:17 +0000 (+0100)
Subject: specials/Memory: allow for more flexibility in memory port signals
X-Git-Tag: 24jan2021_ls180~2099^2~392
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c13fe1bc63b01ea23dd658c343ae3845995d7b45;p=litex.git

specials/Memory: allow for more flexibility in memory port signals
---

diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index ae0a2e63..d048e1bf 100644
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -177,7 +177,10 @@ class _MemoryPort(Special):
 		self.re = re
 		self.we_granularity = we_granularity
 		self.mode = mode
-		self.clock = ClockSignal(clock_domain)
+		if isinstance(clock_domain, str):
+			self.clock = ClockSignal(clock_domain)
+		else:
+			self.clock = clock_domain
 
 	def iter_expressions(self):
 		for attr, target_context in [
@@ -231,7 +234,11 @@ class Memory(Special):
 	@staticmethod
 	def emit_verilog(memory, ns):
 		r = ""
-		gn = ns.get_name # usable instead of verilog_printexpr as ports contain only signals
+		def gn(e):
+			if isinstance(e, Memory):
+				return ns.get_name(e)
+			else:
+				return verilog_printexpr(ns, e)[0]
 		adrbits = bits_for(memory.depth-1)
 		
 		r += "reg [" + str(memory.width-1) + ":0] " \