From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 19 Jun 2020 14:30:45 +0000 (+0100)
Subject: add test_0_moduw and correct name to trunc_rem
X-Git-Tag: div_pipeline~310
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c14c7d918d07fbe529328e7be615d16be9aea140;p=soc.git

add test_0_moduw and correct name to trunc_rem
---

diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index 6446a2df..8bdcd868 100644
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -619,7 +619,7 @@ class PowerParser:
                     if p[2] == '/':
                         fn = 'trunc_div'
                     else:
-                        fn = 'trunc_mod'
+                        fn = 'trunc_rem'
                     # return "function trunc_xxx(l, r)"
                     p[0] =  ast.Call(ast.Name(fn, ast.Load()), (l, r), [])
                 else:
diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py
index b84a10c6..2129de33 100644
--- a/src/soc/simulator/test_div_sim.py
+++ b/src/soc/simulator/test_div_sim.py
@@ -32,6 +32,14 @@ class DivTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
+    def test_0_moduw(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x1234",
+               "moduw  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None):
         initial_regs = [0] * 32