From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 22:55:49 +0000 (-0700)
Subject: D is 25 bits not 24 bits wide
X-Git-Tag: working-ls180~1039^2~81
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c15a35db8487a31592046bfe8422740e196407d1;p=yosys.git

D is 25 bits not 24 bits wide
---

diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v
index 8901b215b..a4256eb92 100644
--- a/techlibs/xilinx/dsp_map.v
+++ b/techlibs/xilinx/dsp_map.v
@@ -32,7 +32,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
 		.A({{5{A[24]}}, A}),
 		.B(B),
 		.C(48'b0),
-		.D(24'b0),
+		.D(25'b0),
 		.P(P_48),
 
 		.INMODE(5'b00000),