From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 16 Jun 2019 19:08:03 +0000 (-0700)
Subject: Try -W 300
X-Git-Tag: working-ls180~1237^2~96
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c15ee827f4a171abe3108dba8f9ad0d7078eb306;p=yosys.git

Try -W 300
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a11648873..45bc47f24 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -25,7 +25,8 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#define XC7_WIRE_DELAY "160"
+#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
+                             // to one LUT6 (instead of a LUT5 + LUT2)
 
 struct SynthXilinxPass : public ScriptPass
 {