From: Paul Mackerras Date: Thu, 14 May 2020 05:41:51 +0000 (+1000) Subject: Merge branch 'mmu' X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c164a2f4eaa5cce2494d3716b2a81e51178ccda7;p=microwatt.git Merge branch 'mmu' Signed-off-by: Paul Mackerras --- c164a2f4eaa5cce2494d3716b2a81e51178ccda7 diff --cc fetch1.vhdl index 301f317,936e830..cb1d1df --- a/fetch1.vhdl +++ b/fetch1.vhdl @@@ -62,11 -62,9 +64,13 @@@ begi v_int := r_int; if rst = '1' then - v.nia := RESET_ADDRESS; + if alt_reset_in = '1' then + v.nia := ALT_RESET_ADDRESS; + else + v.nia := RESET_ADDRESS; + end if; + v.virt_mode := '0'; + v.priv_mode := '1'; v_int.stop_state := RUNNING; elsif e_in.redirect = '1' then v.nia := e_in.redirect_nia; diff --cc icache.vhdl index 3eaf548,86c2746..35d64a8 --- a/icache.vhdl +++ b/icache.vhdl @@@ -385,8 -485,13 +485,13 @@@ begi end loop; -- Generate the "hit" and "miss" signals for the synchronous blocks - req_is_hit <= i_in.req and is_hit and not flush_in and not rst; - req_is_miss <= i_in.req and not is_hit and not flush_in; - if i_in.req = '1' and access_ok = '1' and flush_in = '0' then ++ if i_in.req = '1' and access_ok = '1' and flush_in = '0' and rst = '0' then + req_is_hit <= is_hit; + req_is_miss <= not is_hit; + else + req_is_hit <= '0'; + req_is_miss <= '0'; + end if; req_hit_way <= hit_way; -- The way to replace on a miss