From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 29 May 2019 22:57:19 +0000 (+0100)
Subject: remove FU Dep Cell, go back to SRLatch direct
X-Git-Tag: div_pipeline~1927
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c16bd9fa211f854f5b78aa0ebf15b1ca7ebdd347;p=soc.git

remove FU Dep Cell, go back to SRLatch direct
---

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index 94dc948b..9946dcb5 100644
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -4,44 +4,6 @@ from nmigen import Module, Signal, Const, Elaboratable
 from nmutil.latch import SRLatch
 
 
-class DepCell(Elaboratable):
-    """ FU Dependency Cell
-    """
-    def __init__(self, llen=1):
-        self.llen = llen
-        # inputs
-        self.pend_i = Signal(llen, reset_less=True)    # pending bit in (left)
-        self.issue_i = Signal(llen, reset_less=True)   # Issue in (top)
-        self.go_i = Signal(llen, reset_less=True)      # Go read/write in (left)
-        self.die_i = Signal(llen, reset_less=True)     # Go die in (left)
-
-        # wait
-        self.wait_o = Signal(llen, reset_less=True)  # wait out (right)
-
-    def elaborate(self, platform):
-        m = Module()
-        m.submodules.l = l = SRLatch(sync=False, llen=self.llen) # async latch
-
-        # reset on go HI, set on dest and issue
-        m.d.comb += l.s.eq(self.issue_i & self.pend_i)
-        m.d.comb += l.r.eq(self.go_i | self.die_i)
-
-        # wait out
-        m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i)
-
-        return m
-
-    def __iter__(self):
-        yield self.pend_i
-        yield self.issue_i
-        yield self.go_i
-        yield self.die_i
-        yield self.wait_o
-
-    def ports(self):
-        return list(self)
-
-
 class FUDependenceCell(Elaboratable):
     """ implements 11.4.7 mitch alsup dependence cell, p27
     """
@@ -63,25 +25,24 @@ class FUDependenceCell(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.rd_c = rd_c = DepCell(self.n_fu)
-        m.submodules.wr_c = wr_c = DepCell(self.n_fu)
+        m.submodules.rd_c = rd_c = SRLatch(sync=False, llen=self.n_fu)
+        m.submodules.wr_c = wr_c = SRLatch(sync=False, llen=self.n_fu)
 
-        # connect issue
-        for c in [rd_c, wr_c]:
-            m.d.comb += c.issue_i.eq(self.issue_i)
-            m.d.comb += c.die_i.eq(self.go_die_i)
+        # reset on go HI, set on dest and issue
+        m.d.comb += rd_c.s.eq(self.issue_i & self.rd_pend_i)
+        m.d.comb += wr_c.s.eq(self.issue_i & self.wr_pend_i)
 
         # connect go_rd / go_wr 
-        m.d.comb += wr_c.go_i.eq(self.go_wr_i)
-        m.d.comb += rd_c.go_i.eq(self.go_rd_i)
+        m.d.comb += wr_c.r.eq(self.go_wr_i | self.go_die_i)
+        m.d.comb += rd_c.r.eq(self.go_rd_i | self.go_die_i)
 
         # connect pend_i
-        m.d.comb += wr_c.pend_i.eq(self.wr_pend_i & self.dummy)
-        m.d.comb += rd_c.pend_i.eq(self.rd_pend_i & self.dummy)
+        m.d.comb += rd_c.s.eq(self.issue_i & self.rd_pend_i & self.dummy)
+        m.d.comb += wr_c.s.eq(self.issue_i & self.wr_pend_i & self.dummy)
 
         # connect output
-        m.d.comb += self.wr_wait_o.eq(wr_c.wait_o)
-        m.d.comb += self.rd_wait_o.eq(rd_c.wait_o)
+        m.d.comb += self.rd_wait_o.eq(rd_c.qlq & ~self.issue_i)
+        m.d.comb += self.wr_wait_o.eq(wr_c.qlq & ~self.issue_i)
 
         return m
 
@@ -120,7 +81,7 @@ def dcell_sim(dut):
     yield
 
 def test_dcell():
-    dut = FUDependenceCell()
+    dut = FUDependenceCell(dummy=0, n_fu=4)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_fu_dcell.il", "w") as f:
         f.write(vl)