From: lkcl <lkcl@web>
Date: Sat, 17 Sep 2022 10:16:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~392
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c16f9e31e9f2a4aabb130d5422cd8456eb198885;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 2c575793b..2320557b8 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -755,14 +755,14 @@ Power ISA v3.1 Section 1.6.3 Book I calls it a "defined word".
 
 **SVP64Single:{EXT000-063}** bit6=old  bit7=scalar
 
-This encoding, identical to SVP64Single:{EXT200-263},
-introduces SVP64Single Augmentation of v3.0 Scalar word instructions.
-All meanings must be identical to EXT000 to EXT063, and is is likewise
+This encoding, identical to SVP64Single:{EXT248-263},
+introduces SVP64Single Augmentation of Scalar "defined words".
+All meanings must be identical to EXT000-063, and is is likewise
 prohibited to add an instruction in this area without also adding
 the exact same (non-Augmented) instruction in EXT000-063 with the
 exact same Scalar word.
-PO2 is in the range 0b00000 to 0b11111 to represent EXT000-063 respectively.
-Augmenting EXT001 is prohibited.
+Bits 32-37 0b00000 to 0b11111 represent EXT000-063 respectively.
+Augmenting EXT001 or EXT009 is prohibited.
 
 | 0-5    | 6 | 7 | 8-31  | 32-63   |
 |--------|---|---|-------|---------|
@@ -773,7 +773,7 @@ Augmenting EXT001 is prohibited.
 This encoding is identical to **SVP64:{EXT200-263}** except it
 is the Vectorisation of existing v3.0/3.1 Scalar-words, EXT000-063.
 All the same rules apply with the addition that
-Vectorisation of EXT001 is prohibited.
+Vectorisation of EXT001 or EXT009 is prohibited.
 
 | 0-5    | 6 | 7 | 8-31  | 32-63   |
 |--------|---|---|-------|---------|
@@ -793,7 +793,7 @@ PO2 is in the range 0b11000 to 0b111111 to represent EXT248-263 respectively.
 **SVP64Single:{EXT248-263}** bit6=new bit7=scalar
 
 This encoding, which is effectively "implicit VL=1"
-and comprising (from bits 8-31)
+and comprising (from bits 8-31 being non-zero)
 *at least some* form of Augmentation, it represents the opportunity
 to Augment EXT248-263 with the SVP64Single capabilities.
 Must be allocated under Scalar *and* SVP64 simultaneously.