From: Florent Kermarrec Date: Sat, 20 Dec 2014 15:25:05 +0000 (+0100) Subject: add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems... X-Git-Tag: 24jan2021_ls180~2572^2~82 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c17159754cca2095cd4aa631a0c889430780c8d6;p=litex.git add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems to be stuck in link of command layer) --- diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py index 4dae7d59..1027f434 100644 --- a/lib/sata/command/__init__.py +++ b/lib/sata/command/__init__.py @@ -146,6 +146,8 @@ class SATACommandRX(Module): If(test_type("DMA_ACTIVATE_D2H"), dma_activate.eq(1), NextState("WAIT_WRITE_REG_D2H") + ).Else( + NextState("IDLE") # Generate an error ) ) ) @@ -154,6 +156,8 @@ class SATACommandRX(Module): If(transport.source.stb, If(test_type("REG_D2H"), NextState("PRESENT_WRITE_RESPONSE") + ).Else( + NextState("IDLE") # Generate an error ) ) ) @@ -171,6 +175,8 @@ class SATACommandRX(Module): transport.source.ack.eq(0), If(test_type("DATA"), NextState("PRESENT_READ_DATA") + ).Else( + NextState("IDLE") # Generate an error ) ) ) @@ -189,6 +195,8 @@ class SATACommandRX(Module): If(transport.source.stb, If(test_type("REG_D2H"), NextState("PRESENT_READ_RESPONSE") + ).Else( + NextState("IDLE") # Generate an error ) ) ) diff --git a/test/test_identify.py b/test/test_identify.py index 11cb91cf..24f1a4de 100644 --- a/test/test_identify.py +++ b/test/test_identify.py @@ -7,11 +7,15 @@ mila = MiLaDriver(wb.regs, "mila") wb.open() regs = wb.regs ### + +#trigger0 = mila.sata_con_sink_payload_identify_o*1 +#mask0 = mila.sata_con_sink_payload_identify_m + #trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"] #mask0 = mila.sata_phy_source_source_payload_data_m -trigger0 = mila.sata_con_sink_payload_identify_o*1 -mask0 = mila.sata_con_sink_payload_identify_m +trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"] +mask0 = mila.sata_phy_source_source_payload_data_m mila.prog_term(port=0, trigger=trigger0, mask=mask0) mila.prog_sum("term") diff --git a/test/test_read.py b/test/test_read.py new file mode 100644 index 00000000..155c5487 --- /dev/null +++ b/test/test_read.py @@ -0,0 +1,37 @@ +import time +from config import * +from tools import * +from miscope.host.drivers import MiLaDriver + +mila = MiLaDriver(wb.regs, "mila") +wb.open() +regs = wb.regs +### + +#trigger0 = mila.sata_con_sink_payload_read_o*1 +#mask0 = mila.sata_con_sink_payload_read_m + +#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"] +#mask0 = mila.sata_phy_source_source_payload_data_m + +trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"] +mask0 = mila.sata_phy_source_source_payload_data_m + +mila.prog_term(port=0, trigger=trigger0, mask=mask0) +mila.prog_sum("term") + +# Trigger / wait / receive +mila.trigger(offset=32, length=512) +regs.command_generator_sector.write(0) +regs.command_generator_count.write(1) +regs.command_generator_read.write(1) +mila.wait_done() +mila.read() +mila.export("dump.vcd") +### +wb.close() + +print_link_trace(mila, + tx_data_name="sata_phy_sink_sink_payload_data", + rx_data_name="sata_phy_source_source_payload_data" +) diff --git a/test/test_write.py b/test/test_write.py new file mode 100644 index 00000000..8c760d51 --- /dev/null +++ b/test/test_write.py @@ -0,0 +1,38 @@ +import time +from config import * +from tools import * +from miscope.host.drivers import MiLaDriver + +mila = MiLaDriver(wb.regs, "mila") +wb.open() +regs = wb.regs +### + +#trigger0 = mila.sata_con_sink_payload_write_o*1 +#mask0 = mila.sata_con_sink_payload_write_m + +#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_RDY"] +#mask0 = mila.sata_phy_source_source_payload_data_m + +trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"] +mask0 = mila.sata_phy_source_source_payload_data_m + +mila.prog_term(port=0, trigger=trigger0, mask=mask0) +mila.prog_sum("term") + +# Trigger / wait / receive +mila.trigger(offset=32, length=512) +regs.command_generator_sector.write(0) +regs.command_generator_count.write(1) +regs.command_generator_data.write(0x12345678) +regs.command_generator_write.write(1) +mila.wait_done() +mila.read() +mila.export("dump.vcd") +### +wb.close() + +print_link_trace(mila, + tx_data_name="sata_phy_sink_sink_payload_data", + rx_data_name="sata_phy_source_source_payload_data" +)