From: lkcl <lkcl@web>
Date: Sat, 18 Jun 2022 13:36:33 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1711
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c174698cb07d1c0e9b682dbe9ea38dfcbcd5f784;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index d6c1f99d9..c1a0a6078 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -91,7 +91,7 @@ Pages being developed and examples
   contains explanations and further details
 * [[sv/svp64_quirks]] things in SVP64  that slightly break the rules
 * [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
-* [[sv/vector_comparative_analysis] - a list of Packed SIMD, GPU,
+* [[sv/vector_comparative_analysis]] - a list of Packed SIMD, GPU,
   and other Scalable Vector ISAs
 * [[sv/sprs]] SPRs
 * SVP64 "Modes":