From: Yunsup Lee <yunsup@sifive.com>
Date: Wed, 22 Mar 2017 05:12:37 +0000 (-0700)
Subject: update TLRegisterNode to take Seq of AddressSet
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c1872c574b1e471778ec28e6a782b6547e6917da;p=sifive-blocks.git

update TLRegisterNode to take Seq of AddressSet
---

diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala
index b20b524..5c5b9bf 100644
--- a/src/main/scala/devices/spi/TLSPI.scala
+++ b/src/main/scala/devices/spi/TLSPI.scala
@@ -110,7 +110,7 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
 abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
   require(isPow2(c.rSize))
   val device = new SimpleDevice("spi", Seq("sifive,spi0"))
-  val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w)
+  val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
   val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
 }