From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Sat, 16 Apr 2022 18:39:57 +0000 (-0500)
Subject: Wait one clock after SoC reset drops to start cache access
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c1a38c32b850f96c0d83da0a5cd3c04285271147;p=soc.git

Wait one clock after SoC reset drops to start cache access

When the SoC reset drops, it may take up to one clock cycle
for the issuer to get the core into a known good state with
a valid PC that points to the desired reset vector.  As a
result, there is a risk the ICache starts loading a cache line
from an invalid Wisbbone address, potentially locking the bus
or causing a boot delay.

Wait one clock cycle after the SoC reset drops to start
issuing any instructions, thereby also waiting the same
amount of time to start fetching any instructions.

With the other related commits, this fully fixes Bug #812
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index e41a844c..5bdc77dc 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1152,6 +1152,7 @@ class TestIssuerInternal(TestIssuerBase):
         pdecode2 = self.pdecode2
         cur_state = self.cur_state
         new_svstate = self.new_svstate
+        main_rst_delay = Signal(reset_less=True)
 
         # temporaries
         dec_opcode_i = pdecode2.dec.raw_opcode_in  # raw opcode
@@ -1167,6 +1168,9 @@ class TestIssuerInternal(TestIssuerBase):
         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
         comb += next_dststep.eq(cur_state.svstate.dststep+1)
 
+        # reset release delay
+        sync += main_rst_delay.eq(ResetSignal())
+
         # note if an exception happened.  in a pipelined or OoO design
         # this needs to be accompanied by "shadowing" (or stalling)
         exc_happened = self.core.o.exc_happened
@@ -1195,7 +1199,7 @@ class TestIssuerInternal(TestIssuerBase):
                 sync += pdecode2.instr_fault.eq(0)
                 # wait on "core stop" release, before next fetch
                 # need to do this here, in case we are in a VL==0 loop
-                with m.If(~dbg.core_stop_o & ~core_rst):
+                with m.If(~dbg.core_stop_o & ~core_rst & ~main_rst_delay):
                     sync += fetch_pc_i_valid.eq(1)  # tell fetch to start
                     sync += cur_state.pc.eq(dbg.state.pc)
                     sync += cur_state.svstate.eq(dbg.state.svstate)