From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 28 Feb 2022 17:43:59 +0000 (+0000)
Subject: fix memory issue in yosys synth for icarus
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c1b4b91f252b175da117bd78153b403120a75307;p=ls2.git

fix memory issue in yosys synth for icarus
---

diff --git a/simsoc.ys b/simsoc.ys
index 3bd115f..be21ccb 100644
--- a/simsoc.ys
+++ b/simsoc.ys
@@ -14,6 +14,8 @@ read_verilog  ../uart16550/rtl/verilog/uart_wb.v
 read_verilog  ./external_core_top.v
 
 delete w:$verilog_initial_trigger
+proc
+memory
 proc_prune
 proc_clean
 proc_rmdead
@@ -25,7 +27,11 @@ proc_mux
 proc_rmdead
 proc_clean
 pmuxtree
-memory_collect
+#opt_mem
+#opt_mem_priority
+#opt_mem_feedback
+#opt_clean
+#memory_collect
 extract_fa
 clean
 opt