From: Anuj Phogat Date: Thu, 31 May 2018 22:41:53 +0000 (-0700) Subject: anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c1d8300117891ec87762caa30d14307622c65bcf;p=mesa.git anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat Reviewed-by: Jason Ekstrand Reviewed-by: Lionel Landwerlin --- diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 213b6061278..b1014d9e797 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -121,18 +121,6 @@ genX(init_device_state)(struct anv_device *device) } #endif -#if GEN_GEN == 10 || GEN_GEN == 11 - uint32_t cache_mode_ss; - anv_pack_struct(&cache_mode_ss, GENX(CACHE_MODE_SS), - .FloatBlendOptimizationEnable = true, - .FloatBlendOptimizationEnableMask = true); - - anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { - lri.RegisterOffset = GENX(CACHE_MODE_SS_num); - lri.DataDWord = cache_mode_ss; - } -#endif - anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa); anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {