From: Jason Lowe-Power Date: Fri, 5 Apr 2019 17:29:54 +0000 (-0700) Subject: learning_gem5: Fix vector port panic in SimpleCache X-Git-Tag: v19.0.0.0~978 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c1e646d886096ffeca7d9818316ba5e03391898a;p=gem5.git learning_gem5: Fix vector port panic in SimpleCache Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053 Signed-off-by: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870 Reviewed-by: Anthony Gutierrez --- diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc index 880dc39ad..6deefde53 100644 --- a/src/learning_gem5/part2/simple_cache.cc +++ b/src/learning_gem5/part2/simple_cache.cc @@ -54,10 +54,10 @@ SimpleCache::SimpleCache(SimpleCacheParams *params) : Port & SimpleCache::getPort(const std::string &if_name, PortID idx) { - panic_if(idx != InvalidPortID, "This object doesn't support vector ports"); - // This is the name from the Python SimObject declaration in SimpleCache.py if (if_name == "mem_side") { + panic_if(idx != InvalidPortID, + "Mem side of simple cache not a vector port"); return memPort; } else if (if_name == "cpu_side" && idx < cpuPorts.size()) { // We should have already created all of the ports in the constructor