From: lkcl <lkcl@web>
Date: Tue, 3 May 2022 17:03:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2501
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c1ea0549ceba27de63d22500bf04fc5b42f8c2a9;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 73fd79245..4330a2fb9 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -52,7 +52,7 @@ ternlog has its own major opcode
 |  -00   |1 | grevlog   |
 |  -01   |  | crternlog  |
 |  010   |Rc| bitmask   |
-|  011   |  | gf/cl madd*  |
+|  011   |  | SVP64  |
 |  110   |Rc| 1/2-op    |
 |  111   |  | bmrevi   |
 
@@ -103,6 +103,7 @@ TODO: convert all instructions to use RT and not RS
 | NN |    |     |      |         | 01    011 |1 | rsvd |
 | NN |    |     |      |         | 10    011 |Rc| svstep |
 | NN |    |     |      |         | 11    011 |Rc| setvl |
+| NN |    |     |      |         | ..... 110 |  | 1/2 ops |
 | NN | RT | RA  | RB   | sh0-4   | sh5 1 111 |Rc| bmrevi |
 
 ops (note that av avg and abs as well as vec scalar mask