From: Tsukasa OI Date: Sun, 7 Aug 2022 05:57:00 +0000 (+0900) Subject: RISC-V: Add macro-only operands to validate_riscv_insn X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c1ecdee7e09681096229c177bb5fba8a538ce446;p=binutils-gdb.git RISC-V: Add macro-only operands to validate_riscv_insn Although they are not (and should not be) reachable, following macro-only operands are parsed in the `validate_riscv_insn' function and ignored. That function also notes that they are macro-only. - "A" - "B" - "I" Following this convention, this commit adds three remaining macro-only operands to this function. By doing this, we could instead choose to reject those operands from appearing in regular instructions later. - "c" (used by call, tail and jump macros) - "VM" (used by vmsge.vx and vmsgeu.vx macros) - "VT" (likewise) gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add "c", "VM" and "VT" macro-only operand types. --- diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 5411d68a401..0a14b2cecc8 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1203,6 +1203,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'j': case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break; case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break; + case 'M': break; /* Macro operand, must be a mask register. */ + case 'T': break; /* Macro operand, must be a vector register. */ default: goto unknown_validate_operand; } @@ -1214,6 +1216,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case 'A': break; /* Macro operand, must be symbol. */ case 'B': break; /* Macro operand, must be symbol or constant. */ + case 'c': break; /* Macro operand, must be symbol or constant. */ case 'I': break; /* Macro operand, must be constant. */ case 'D': /* RD, floating point. */ case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;