From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 18 Mar 2022 09:26:46 +0000 (+0000)
Subject: whitespace cleanup and make SPI core (temporarily) optional
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c1f4327be04901c0291e96c063e2df8f9cf311de;p=ls2.git

whitespace cleanup and make SPI core (temporarily) optional
based on arctic tern fpga board. TODO: add arctic tern fpga board to
nmigen_boards
---

diff --git a/src/ls2.py b/src/ls2.py
index e67e1ef..3adbc73 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -371,22 +371,25 @@ class DDR3SoC(SoC, Elaboratable):
 
         # SPI controller
         if spi_0_pins is not None or fpga == 'sim':
-            # The Lattice ECP5 devices require special handling on the dedicated SPI clock line,
-            # which is shared with the internal SPI controller used for FPGA bitstream loading.
+            # The Lattice ECP5 devices require special handling on the
+            # dedicated SPI clock line, which is shared with the internal
+            # SPI controller used for FPGA bitstream loading.
             spi0_is_lattice_ecp5_clk = False
-            if platform is not None and fpga in ['versa_ecp5', 'rcs_arctic_tern_bmc_card', 'isim']:
+            if platform is not None and fpga in ['versa_ecp5',
+                                                 'rcs_arctic_tern_bmc_card',
+                                                 'isim']:
                 spi0_is_lattice_ecp5_clk = True
 
-            # Tercel contains two independent Wishbone regions, a configuration
-            # region and the direct API access region,
-            # Set the SPI 0 access region to 16MB, as the FPGA bitstream Flash device
-            # is unlikely to be larger than this.
-            # The main SPI Flash (SPI 1) should be set to at least 28 bits (256MB) to
-            # allow the use of large 4BA devices.
+            # Tercel contains two independent Wishbone regions, a
+            # configuration region and the direct API access region,
+            # Set the SPI 0 access region to 16MB, as the FPGA
+            # bitstream Flash device is unlikely to be larger than this.
+            # The main SPI Flash (SPI 1) should be set to at
+            # least 28 bits (256MB) to allow the use of large 4BA devices.
             self.spi0 = Tercel(data_width=32, spi_region_addr_width=24,
-                                            clk_freq=clk_freq,
-                                            pins=spi_0_pins,
-                                            lattice_ecp5_usrmclk=spi0_is_lattice_ecp5_clk)
+                               clk_freq=clk_freq,
+                               pins=spi_0_pins,
+                               lattice_ecp5_usrmclk=spi0_is_lattice_ecp5_clk)
             self._decoder.add(self.spi0.bus, addr=spi0_addr)
             self._decoder.add(self.spi0.cfg_bus, addr=spi0_cfg_addr)
 
@@ -573,9 +576,11 @@ if __name__ == "__main__":
                                          "cs": 4})
 
     # Get SPI resource pins
-    if platform is not None:
+    spi_0_pins = None
+    if platform is not None and fpga in ['rcs_arctic_tern_bmc_card']:
         if toolchain == 'Trellis':
-            # The ECP5 series FPGAs handle the SPI clock directly on the FPGA configuration Flash device
+            # The ECP5 series FPGAs handle the SPI clock directly on
+            # the FPGA configuration Flash device
             spi_0_pins = platform.request("spi_0", 0,
                                         dir={"dq":"io", "cs_n":"o"},
                                         xdr={"dq": 1, "cs_n": 1})