From: georgerennie <georgerennie@gmail.com>
Date: Tue, 1 Dec 2020 01:37:19 +0000 (+0000)
Subject: Fix SYNTHESIS always being defined in Verilog frontend
X-Git-Tag: working-ls180~184^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c1f6ce8b33b1c06a4e38b621e27876d5715eb26d;p=yosys.git

Fix SYNTHESIS always being defined in Verilog frontend
---

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index ea23139e2..752f7a7a8 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -321,7 +321,6 @@ struct define_body_t
 define_map_t::define_map_t()
 {
 	add("YOSYS", "1");
-	add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
 }
 
 // We must define this destructor here (rather than relying on the default), because we need to
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 2e9c9b2e2..5319a45ad 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -446,6 +446,9 @@ struct VerilogFrontend : public Frontend {
 			}
 			break;
 		}
+
+		defines_map.add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
+
 		extra_args(f, filename, args, argidx);
 
 		log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());