From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 8 Aug 2017 03:46:00 +0000 (-0700)
Subject: Fixed typo in error message
X-Git-Tag: yosys-0.8~346^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c205d571df90b7bdca5207e441dec5e1dabdc2ed;p=yosys.git

Fixed typo in error message
---

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 30fbef9f2..cda83862a 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -80,7 +80,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
 			"BOTH": begin
 				initial begin
-					$display("Both-edge reset mode for GP_COUNT8 not implemented");
+					$display("Both-edge reset mode for GP_COUNT14 not implemented");
 					$finish;
 				end
 			end