From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Nov 2021 10:28:46 +0000 (+0000)
Subject: whoops, hazard vectors were depth 1 width N
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c20db46a9eb0a17de2ccb471ea72b669a641b914;p=soc.git

whoops, hazard vectors were depth 1 width N
they need to be regwidth 1 (1 bit wide) depth N (one per register)
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 93d94226..8461181a 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -285,9 +285,9 @@ class RegFiles:
 
     def make_hazard_vec(self, rf, name):
         if isinstance(rf, VirtualRegPort):
-            vec = RegFileArray(rf.bitwidth, 1)
+            vec = RegFileArray(1, rf.nregs)
         else:
-            vec = RegFileArray(rf.depth, 1)
+            vec = RegFileArray(1, rf.depth)
         # get read/write port specs and create bitvector ports with same names
         wr_spec, rd_spec = rf.get_port_specs()
         create_ports(vec, wr_spec, rd_spec)