From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 16 May 2020 21:54:13 +0000 (+0100)
Subject: add shift pipeline operand in/out table
X-Git-Tag: convert-csv-opcode-to-binary~2651
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2177c47de6c6e95e4f2bdcec29adf73285f370f;p=libreriscv.git

add shift pipeline operand in/out table
---

diff --git a/3d_gpu/architecture/pipeline_operands.mdwn b/3d_gpu/architecture/pipeline_operands.mdwn
index 21d47cd61..568b7dce6 100644
--- a/3d_gpu/architecture/pipeline_operands.mdwn
+++ b/3d_gpu/architecture/pipeline_operands.mdwn
@@ -100,3 +100,19 @@ Output:
     RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
 '''
 
+# Shift Register Pipeline
+
+Input:
+'''
+    64 - Port 1   64 - Port 2  64 - Port 3  1 - SO  1 - Carry
+    -----------   -----------  -----------  ------  ---------
+    RA            RB/immed     RS           so      carry_in
+'''
+
+Output:
+'''
+    64 - Port 1   4 - Port 2   1 - SO  2 - Carry/Carry32 2 - OV/OV32
+    -----------   -----------  ------  ----------------- -----------
+    RC/RT         CR0          so      cr_o / cr32_o     ov_o / ov32_o
+'''
+