From: Florent Kermarrec Date: Sun, 1 Mar 2015 10:24:58 +0000 (+0100) Subject: liteXXX cores: remove Identifier duplication X-Git-Tag: 24jan2021_ls180~2550 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c21a7956c8f7aa21f77972ffc65cff44945501d4;p=litex.git liteXXX cores: remove Identifier duplication --- diff --git a/misoclib/com/liteeth/example_designs/targets/__init__.py b/misoclib/com/liteeth/example_designs/targets/__init__.py index 75aca863..e69de29b 100644 --- a/misoclib/com/liteeth/example_designs/targets/__init__.py +++ b/misoclib/com/liteeth/example_designs/targets/__init__.py @@ -1,26 +0,0 @@ -import subprocess - -from migen.fhdl.std import * -from migen.bank.description import * - -def get_id(): - output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii") - return int(output[:8], 16) - -class Identifier(Module, AutoCSR): - def __init__(self, sysid, frequency, revision=None): - self._sysid = CSRStatus(16) - self._revision = CSRStatus(32) - self._frequency = CSRStatus(32) - - ### - - if revision is None: - revision = get_id() - - self.comb += [ - self._sysid.status.eq(sysid), - self._revision.status.eq(revision), - self._frequency.status.eq(frequency), - ] - diff --git a/misoclib/mem/litesata/example_designs/targets/__init__.py b/misoclib/mem/litesata/example_designs/targets/__init__.py index 85efe5d9..e69de29b 100644 --- a/misoclib/mem/litesata/example_designs/targets/__init__.py +++ b/misoclib/mem/litesata/example_designs/targets/__init__.py @@ -1,26 +0,0 @@ -import subprocess - -from migen.fhdl.std import * -from migen.bank.description import * - -def get_id(): - output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii") - return int(output[:8], 16) - -class Identifier(Module, AutoCSR): - def __init__(self, sysid, frequency, revision=None): - self._r_sysid = CSRStatus(16) - self._r_revision = CSRStatus(32) - self._r_frequency = CSRStatus(32) - - ### - - if revision is None: - revision = get_id() - - self.comb += [ - self._r_sysid.status.eq(sysid), - self._r_revision.status.eq(revision), - self._r_frequency.status.eq(frequency), - ] - diff --git a/misoclib/tools/litescope/example_designs/targets/__init__.py b/misoclib/tools/litescope/example_designs/targets/__init__.py index 85efe5d9..e69de29b 100644 --- a/misoclib/tools/litescope/example_designs/targets/__init__.py +++ b/misoclib/tools/litescope/example_designs/targets/__init__.py @@ -1,26 +0,0 @@ -import subprocess - -from migen.fhdl.std import * -from migen.bank.description import * - -def get_id(): - output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii") - return int(output[:8], 16) - -class Identifier(Module, AutoCSR): - def __init__(self, sysid, frequency, revision=None): - self._r_sysid = CSRStatus(16) - self._r_revision = CSRStatus(32) - self._r_frequency = CSRStatus(32) - - ### - - if revision is None: - revision = get_id() - - self.comb += [ - self._r_sysid.status.eq(sysid), - self._r_revision.status.eq(revision), - self._r_frequency.status.eq(frequency), - ] -