From: lkcl <lkcl@web>
Date: Mon, 20 Jun 2022 11:04:53 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c225f7481d12f258dcea9301b7d9b1c94c37b808;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 0c4197522..d22dfb5bc 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -207,36 +207,11 @@ The vector mask set-including-first instruction is similar to set-before-first,
                        vmsif.m v2, v3, v0.t
      1 1 x x x x 1 1   v2 contents
 
-Pseudo-code:
-
-    def sif(rd, rs1, rs2):
-        rd = 0
-        setting_mode = rs2 == x0 or (regs[rs2] & 1)
-
-        while i < XLEN:
-            bit = 1<<i
-
-            # only reenable when predicate in use, and bit valid
-            if !setting_mode && rs2 != x0:
-                if (regs[rs2] & bit):
-                    # back into "setting" mode
-                    setting_mode = True
-
-            # skipping mode
-            if !setting_mode:
-                # skip any more 1s
-                if regs[rs1] & bit == 1:
-                    i += 1
-                    continue
-
-            # setting mode, search for 1
-            regs[rd] |= bit # always set during search
-            if regs[rs1] & bit: # found a bit in rs1:
-                setting_mode = False
-                # next loop starts skipping
-
-            i += 1
+Executable demo:
 
+```
+[[!inline quick="yes" raw="yes" pages="openpower/sv/sbf.py"]]
+```
 
 ## vmsof