From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 24 Dec 2020 00:25:40 +0000 (+0000)
Subject: updating sv_analys.py svp64 table
X-Git-Tag: convert-csv-opcode-to-binary~989
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c238e052815d2fd676a8b37153b061e40a9946d5;p=libreriscv.git

updating sv_analys.py svp64 table
---

diff --git a/openpower/opcode_regs_deduped.mdwn b/openpower/opcode_regs_deduped.mdwn
index 167169671..cfc3dd65d 100644
--- a/openpower/opcode_regs_deduped.mdwn
+++ b/openpower/opcode_regs_deduped.mdwn
@@ -975,9 +975,9 @@ divwo | 1P | EXTRA3 | d:RT,d:CR0 | s:RA | s:RB |  | RA | RB | NONE | RT | NONE |
 
 [[!table  data="""
 insn | Ptype | Etype | 0 | 1 | 2 | 3 |
-rlwimi | 1P | EXTRA3 | TODO |  |  |  | RA |  | RS | RA | NONE | CR0 |
-rldimi | 1P | EXTRA3 | TODO |  |  |  | RA |  | RS | RA | NONE | CR0 |
-rldimi | 1P | EXTRA3 | TODO |  |  |  | RA |  | RS | RA | NONE | CR0 |
+rlwimi | 1P | EXTRA3 | d:RA,d:CR0 | s:RA | s:RS |  | RA |  | RS | RA | NONE | CR0 |
+rldimi | 1P | EXTRA3 | d:RA,d:CR0 | s:RA | s:RS |  | RA |  | RS | RA | NONE | CR0 |
+rldimi | 1P | EXTRA3 | d:RA,d:CR0 | s:RA | s:RS |  | RA |  | RS | RA | NONE | CR0 |
 """]]
 
 ## 2R-1W-CRi (RM-1P-3S1D)
diff --git a/openpower/sv_analysis.py b/openpower/sv_analysis.py
index 82ea36847..6fb50d7cb 100644
--- a/openpower/sv_analysis.py
+++ b/openpower/sv_analysis.py
@@ -455,7 +455,8 @@ def process_csvs():
                     res['0'] = 'd:BF' # BF: Rdest1_EXTRA3
                     res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
                     res['2'] = 's:RB' # RB: Rsrc1_EXTRA3
-                elif regs == ['','RB','RS','RA','','CR0']:
+                elif (regs == ['','RB','RS','RA','','CR0'] or
+                      regs == ['','RB','RS','RA','','CR0']):
                     res['0'] = 'd:RA,d:CR0' # RA,CR0: Rdest1_EXTRA3
                     res['1'] = 's:RB' # RB: Rsrc1_EXTRA3
                     res['2'] = 's:RS' # RS: Rsrc1_EXTRA3
@@ -463,6 +464,10 @@ def process_csvs():
                     res['0'] = 'd:RT,d:CR0' # RT,CR0: Rdest1_EXTRA3
                     res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
                     res['2'] = 's:RB' # RB: Rsrc1_EXTRA3
+                elif regs == ['RA','','RS','RA','','CR0']:
+                    res['0'] = 'd:RA,d:CR0' # RA,CR0: Rdest1_EXTRA3
+                    res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
+                    res['2'] = 's:RS' # RS: Rsrc1_EXTRA3
                 else:
                     res['0'] = 'TODO'