From: lkcl <lkcl@web>
Date: Wed, 14 Sep 2022 21:06:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~437
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c239701e77907a9900693c80d3f46ec4c0dab582;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 08f6743f9..20443bfd7 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -160,7 +160,10 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 # Simple-V Architectural Resources
 
 * No new Interrupt types are required.
-  (**No modifications to existing Power ISA opcodes are required either**).
+* No modifications to existing Power ISA opcodes are required either.
+* No new Register Files are required (because Simple-V is a category of
+  Zero-Overhead Looping on top of existing instructions and
+  existing registers, not an actual Vector ISA)
 * GPR FPR and CR Field Register extend to 128.  A future
   version may extend to 256 or beyond[^extend] or also extend VSX[^futurevsx]
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)