From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Jun 2020 16:46:33 +0000 (+0100)
Subject: update test_sim.py to do a simple execution loop: decode-execute-decode-execute
X-Git-Tag: div_pipeline~337
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c24d08dab15a11dda7c503c989fb30033dc90cfa;p=soc.git

update test_sim.py to do a simple execution loop: decode-execute-decode-execute
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index c62a32c3..1dd5a9bc 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -76,13 +76,15 @@ class Mem:
         return shifter, mask
 
     # TODO: Implement ld/st of lesser width
-    def ld(self, address, width=8, swap=True):
+    def ld(self, address, width=8, swap=True, check_in_mem=False):
         print("ld from addr 0x{:x} width {:d}".format(address, width))
         remainder = address & (self.bytes_per_word - 1)
         address = address >> self.word_log2
         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
         if address in self.mem:
             val = self.mem[address]
+        elif check_in_mem:
+            return None
         else:
             val = 0
         print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
@@ -229,11 +231,10 @@ class ISACaller:
         print ("ISACaller insns", respect_pc, initial_insns, disassembly)
 
         # "fake program counter" mode (for unit testing)
+        self.fake_pc = 0
         if not respect_pc:
             if isinstance(initial_mem, tuple):
                 self.fake_pc = initial_mem[0]
-            else:
-                self.fake_pc = 0
 
         # disassembly: we need this for now (not given from the decoder)
         self.disassembly = {}
@@ -402,8 +403,11 @@ class ISACaller:
         else:
             pc = self.fake_pc
         self._pc = pc
-        ins = self.imem.ld(pc, 4, False)
+        ins = self.imem.ld(pc, 4, False, True)
+        if ins is None:
+            raise KeyError("no instruction at 0x%x" % pc)
         print("setup: 0x{:X} 0x{:X}".format(pc, ins & 0xffffffff))
+        print ("NIA, CIA", self.pc.CIA.value, self.pc.NIA.value)
 
         yield self.dec2.dec.raw_opcode_in.eq(ins)
         yield self.dec2.dec.bigendian.eq(0)  # little / big?
@@ -419,6 +423,7 @@ class ISACaller:
 
         if not self.respect_pc:
             self.fake_pc += 4
+        print ("NIA, CIA", self.pc.CIA.value, self.pc.NIA.value)
 
     def call(self, name):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 95d5c75f..cf213f69 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -24,34 +24,29 @@ class DecoderTestCase(FHDLTestCase):
     def run_tst(self, generator, initial_mem=None):
         m = Module()
         comb = m.d.comb
-        instruction = Signal(32)
 
-        pdecode = create_pdecode()
+        gen = list(generator.generate_instructions())
+        insn_code = generator.assembly.splitlines()
+        instructions = list(zip(gen, insn_code))
 
+        pdecode = create_pdecode()
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
-        simulator = ISA(pdecode2, [0] * 32, {}, 0, initial_mem, 0)
-        comb += pdecode2.dec.raw_opcode_in.eq(instruction)
-        comb += pdecode2.dec.bigendian.eq(0)
-        gen = generator.generate_instructions()
-        instructions = list(zip(gen, generator.assembly.splitlines()))
+        simulator = ISA(pdecode2, [0] * 32, {}, 0, initial_mem, 0,
+                        initial_insns=gen, respect_pc=True,
+                        disassembly=insn_code)
 
         sim = Simulator(m)
-        def process():
-
-            index = simulator.pc.CIA.value//4
-            while index < len(instructions):
-                ins, code = instructions[index]
 
-                print("0x{:X}".format(ins & 0xffffffff))
-                print(code)
-
-                yield instruction.eq(ins)
-                yield Delay(1e-6)
-
-                opname = code.split(' ')[0]
-                yield from simulator.call(opname)
-                index = simulator.pc.CIA.value//4
+        def process():
+            while True:
+                try:
+                    yield from simulator.setup_one()
+                except KeyError: # indicates instruction not in imem: stop
+                    break
+                yield Settle()
+                yield from simulator.execute_one()
+                yield Settle()
 
 
         sim.add_process(process)