From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 19 Apr 2019 01:05:01 +0000 (+0100)
Subject: update comments
X-Git-Tag: div_pipeline~2221
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2525b9882d1ae653704cb8d3072c7d289c9bdb8;p=soc.git

update comments
---

diff --git a/TLB/src/ariane/ptw.py b/TLB/src/ariane/ptw.py
index 8bd3cbea..373b93f0 100644
--- a/TLB/src/ariane/ptw.py
+++ b/TLB/src/ariane/ptw.py
@@ -55,7 +55,7 @@ class DCacheReqO:
     def __init__(self):
         self.data_gnt = Signal()
         self.data_rvalid = Signal()
-        self.data_rdata = Signal(64)
+        self.data_rdata = Signal(64) # actually in PTE object format
 
     def ports(self):
         return [ self.data_gnt, self.data_rvalid, self.data_rdata]
@@ -113,6 +113,7 @@ class TLBUpdate:
         return [self.valid, self.is_2M, self.is_1G, self.vpn, self.asid] + \
                 self.content.ports()
 
+
 # SV39 defines three levels of page tables
 LVL1 = Const(0, 2) # defined to 0 so that ptw_lvl default-resets to LVL1
 LVL2 = Const(1, 2)
@@ -179,6 +180,8 @@ class PTW:
         data_rvalid = Signal()
         data_rdata = Signal(64)
 
+        # NOTE: pte decodes the incoming bit-field (data_rdata). data_rdata
+        # is spec'd in 64-bit binary-format: better to spec as Record?
         pte = PTE()
         m.d.comb += pte.flatten().eq(data_rdata)