From: Luke Kenneth Casson Leighton Date: Mon, 20 Jun 2022 20:05:19 +0000 (+0100) Subject: add SWAR acronym X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2726b78635427b8dcf44d5863b222fc21156c10;p=libreriscv.git add SWAR acronym --- diff --git a/svp64-primer/acronyms.tex b/svp64-primer/acronyms.tex index 66b8ba494..99d848554 100644 --- a/svp64-primer/acronyms.tex +++ b/svp64-primer/acronyms.tex @@ -12,6 +12,7 @@ \acro{MMX}{Intel's first SIMD implementation} \acro{RVV}{RISC-V Vector extension} \acro{SIMD}{Single Instruction Multiple Data} + \acro{SWAR}{SIMD Within A Register (see Flynn's Taxonomy)} \acro{SV}{(Scalable) Simple Vectorisation or Simple-V} \acro{SVE2}{ARM Scalable Vector Extension version two} \acro{SVP64}{Simple-V with Prefixing of Power ISA, 64-bits in length} diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex index d71686a80..2dd482882 100644 --- a/svp64-primer/summary.tex +++ b/svp64-primer/summary.tex @@ -53,8 +53,9 @@ the Power ISA's Supercomputing pedigree. registers of 64-bit length into smaller 8-, 16-, 32-bit pieces. \cite{SIMD_HARM}\cite{SIMD_HPC} These partitions can then be operated on simultaneously, and the initial values -and results being stored as entire 64-bit registers. The SIMD instruction opcode - includes the data width and the operation to perform. +and results being stored as entire 64-bit registers (\acs{SWAR}). +The SIMD instruction opcode +includes the data width and the operation to perform. \par \begin{figure}[hb]